Timing Design Engineer

Apple is seeking an ASIC STA Engineer to contribute to the design and timing aspects of System on Chip (SoC) development. This role emphasizes collaboration, innovation, and the importance of diverse perspectives in achieving high-quality outcomes. The engineer will be responsible for timing sign-off, developing sign-off flows, and managing timing constraints to ensure successful project completion.

Responsibilities:

• Perform timing sign-off for SoC designs.
• Develop STA and sign-off flows.
• Own IP and block level timing constraints for both regular and custom requirements.
• Collaborate with RTL designers to understand design intent and clock structure.
• Work with CAD teams to develop and refine timing flows.
• Engage with the Physical design team to close and sign-off timing.
• Innovate timing constraints and flows to facilitate timing closure.
• Verify timing constraints and address potential issues in timing analysis.

Qualifications:

• BS degree in a technical discipline.
• Minimum 10 years of relevant experience in ASIC design.

Skills:

• Proven knowledge of ASIC timing closure flow and methodology.
• 2+ years of experience in writing ASIC timing constraints and achieving timing closure.
• Expertise in STA tools, particularly Primetime.
• Understanding of timing corners/modes, process variations, and signal integrity issues.
• Hands-on experience in timing/SDC constraints generation and management.
• Proficient in scripting languages such as Tcl and Perl.
• Familiarity with synthesis, DFT, and backend methodologies and tools.
• Strong communication skills for effective collaboration across diverse teams.