TPU Compute RTL Design Engineer

Join Google's innovative team as an ASIC Design Engineer, where you'll develop custom silicon solutions that enhance the performance of direct-to-consumer products. Your work will contribute to the next generation of hardware experiences, focusing on efficiency and integration in data center accelerators.

Responsibilities:

• Create and review microarchitecture specifications for the compute subsystem design.
• Define integration requirements for the compute subsystem to the System on Chip (SoC).
• Develop SystemVerilog RTL to implement logic for ASIC products, adhering to coding and quality guidelines.
• Collaborate with design validation teams to create test plans for verifying and debugging design RTL.
• Work with physical design teams to ensure designs meet physical requirements and achieve timing closure.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in digital design using SystemVerilog RTL.
• Experience with power, performance, and area optimizations.

Skills:

• Experience collaborating with software, architecture, and physical design teams.
• Knowledge of processor design, accelerators, or memory hierarchies.