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Semiconductor IP Core Companies & Vendors Directory A–Z

Explore our alphabetical directory of semiconductor IP core companies and silicon IP vendors for ASIC and system-on-chip (SoC) design. Find companies working with processor IP, interface IP, memory IP, analog and mixed-signal IP, security IP, and other reusable semiconductor design blocks.
 
Whether you are evaluating third-party IP for an

Ramtera Challenges the Cost of Chip Design with LVR and PRE: Calibre-Correlated Physical Verification and an Integrated Place-and-Route Solution

For semiconductor design teams, the challenge is not simply completing a layout. It is getting there with predictable verification results, manageable tool costs and support when a project approaches tapeout. Ramtera Design Automation is addressing those needs with two complementary electronic design automation (EDA) engines: LVR for physical verification and

The History of SMIC: China’s Rise in Semiconductor Manufacturing

Semiconductor Manufacturing International Corporation (SMIC) is one of the most important companies in the development of China’s semiconductor industry. Founded in Shanghai in 2000 by Taiwanese semiconductor executive Richard Chang, SMIC emerged with an ambitious objective: to establish a world-class semiconductor foundry capable of competing with established manufacturers such as

The History of UMC: From Taiwan’s Semiconductor Beginnings to a Global Foundry

United Microelectronics Corporation (UMC) is one of the pioneering companies in Taiwan’s semiconductor industry and an important participant in the development of the global semiconductor foundry business. Established in 1980 with support from the Taiwanese government, UMC emerged during a period when Taiwan was attempting to transform its economy from

The History of GlobalFoundries: From AMD to a Global Semiconductor Foundry

The history of GlobalFoundries is a story about one of the semiconductor industry’s most important transformations: the separation of chip design from semiconductor manufacturing.
 
Established in 2009 following the separation of AMD’s manufacturing operations, GlobalFoundries entered the market with an ambitious objective: to become a major competitor to Taiwan

EU launches €525 million chip design platform to boost startups

Nov-5-2026 — The European Commission has launched the European Chip Design Platform (EuroCDP), backed by €525 million in investment to support a new generation of European semiconductor design companies. The initiative, launched by Henna Virkkunen, Executive Vice-President for Tech Sovereignty, Security and Democracy, is a key part of the EU

ElectraIC Avionics IP Cores for FPGA: MIL-STD-1553B, ARINC 429 and ARINC 664

AnySilicon IP Vendor Spotlight: Avionics communication interfaces demand precise timing, dependable data handling and extensive verification. For FPGA design teams, developing these protocol functions from scratch can add significant integration and validation effort.
 
In this spotlight, Ates Berna, General Manager and Managing Partner of ElectraIC, introduces the company’s

Changing Wafer Foundries: Costs, Timeline, Risks and Qualification Checklist

Moving an existing ASIC or semiconductor product to another wafer fab can lower manufacturing cost, improve supply continuity and reduce geopolitical exposure. But a foundry transfer is rarely a simple matter of sending the same masks to a different factory. Here is how to assess technical feasibility, budget

Semiconductor IP Deliverables: What Should an IP Supplier Provide?

A semiconductor intellectual property (IP) core becomes useful to a chip design team when the team can install it, understand its behavior, verify its configuration, and connect it to the rest of the system. Delivering the design itself is only part of that handoff. The supporting files determine how much

How to Evaluate Semiconductor IP Before Integrating It into Your SoC

Choosing semiconductor intellectual property (IP) is a decision about the entire chip development process. A core may provide the required function yet still create substantial work when its interfaces, timing assumptions, verification models, or physical characteristics do not fit the system.

 
For an engineering team developing a system-on-chip