Semiconductor Latest News

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Full-Service Foundry: accelerate your analog mixed-signal prototyping with the 2026 MPW calendar

wafer

The ams OSRAM 2026 MPW (Multi-Project Wafer) program expands its technology offering with new 180nm options, including the C18 CMOS specialty platform further enriching the MPW portfolio. For mixed-signal designs in mature nodes, this extension delivers strong analog, high-voltage and BCD capabilities tailored to customer needs.
 
The MPW program

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CEO Talk: Uttam Singhal of SignOff Semiconductors

This interview features: Uttam Singhal, CEO, SignOff Semiconductors Pvt. Ltd.
 

 
Tell me a bit about your background? How did you first get started with your company?
I have spent over 25 years in the semiconductor industry, beginning my career in full-custom analog and memory design before transitioning

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28nm vs 40nm vs 65nm — The Real Cost, Risk, and Power Trade-Off for ASICs

press release wafer

Choosing between 28nm, 40nm, and 65nm is one of the most common — and most underestimated — decisions in ASIC development.
 
These nodes dominate industrial, automotive, consumer, and IoT ASICs, yet teams often choose based on habit or outdated assumptions. In reality, the differences between 28nm, 40nm, and 65nm

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TSMC 22nm vs UMC 22nm vs GF 22FDX — Which Should You Choose?

press release wafer

Choosing a 22nm process node is not just a scaling decision — it is a strategic choice that affects power consumption, cost structure, ecosystem access, and long-term product risk.
 
For many ASIC and SoC teams, 22nm sits at the crossroads between mature nodes (28nm/40nm) and more advanced, higher-risk technologies.

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Exclusive Interview: Mika Jäsberg Discusses CoreHW’s RTLS Offering

In this exclusive interview, Mika Jäsberg, Head of Sourcing, Manufacturing, and Operations at CoreHW, shares insights into the company’s next-generation real-time location system (RTLS). He discusses CoreRTLS Tag series, CoreRTLS-LOC4000, and CoreRTLS software—highlighting innovations in accuracy, scalability, and security that position CoreHW as a leader in location intelligence technology.
 

 
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Find a Local Semiconductor/ASIC/IP Sales Representative (Asia, Europe, US)

Two funny scientists

AnySilicon helps you connect with experienced sales agents, reps, and local partners across Asia, Europe, and the US — at no cost.
 
Expanding into a new market is hard—especially in semiconductors. Cultural gaps, language barriers, and the challenge of finding trusted local representation often slow things down.
AnySilicon offers

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The Future of Semiconductors: A Deep Dive with Howard Pakosh

Howard Pakosh Interview

This interview features Howard Pakosh,  CEO & Founder at The TekStart Group.
 

 
Can you describe your company’s founding vision and how it has evolved to address the changing landscape of the semiconductor industry?
When I founded TekStart® back in 1998, the idea was simple but ambitious. Take

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Innovation Meets Customization: Unlocking breakthroughs in next-gen sensing 

Discover how ams OSRAM’s ASIC customization, in-silicon innovation, and advanced packaging deliver reliable, efficient and high-performance sensing solutions for industrial and medical applications. 
 
Customization to meet power, reliability, and integration needs in next-gen sensing 
Across the industrial and medical sectors, engineers and product leaders face the same persistent dilemma: how to deliver smarter, more

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28nm Wafer & MPW Cost Explained: Constraints, Risk, and When It Makes Sense

wafer

28nm is a turning point in ASIC development. It is often described as a “mature advanced node,” but in practice it represents the last node where many non-hyperscale teams can realistically operate. Beyond 28nm, ASIC economics, risk, and organizational requirements change dramatically.
 
This article explains what drives 28nm wafer and

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40nm Wafer & MPW Cost Explained: Constraints, Risk, and When It Makes Sense

wafer

40nm is often the first node where advanced-node realities become unavoidable. While still planar, 40nm introduces a level of complexity, cost sensitivity, and schedule risk that is very different from 55nm and above. As a result, cost assumptions at 40nm are frequently optimistic — especially for first-time ASIC teams.
 
This

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