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28nm is a turning point in ASIC development. It is often described as a “mature advanced node,” but in practice it represents the last node where many non-hyperscale teams can realistically operate. Beyond 28nm, ASIC economics, risk, and organizational requirements change dramatically.
This article explains what drives 28nm wafer and
40nm is often the first node where advanced-node realities become unavoidable. While still planar, 40nm introduces a level of complexity, cost sensitivity, and schedule risk that is very different from 55nm and above. As a result, cost assumptions at 40nm are frequently optimistic — especially for first-time ASIC teams.
This
55nm sits firmly in the advanced planar node category. While it is often grouped with 65nm, in practice it behaves very differently — especially in terms of cost sensitivity, schedule risk, and MPW limitations.
This article explains what drives 55nm wafer and MPW cost, and when MPW is still
90nm is often misunderstood. It is sometimes treated like a “slightly smaller 130nm,” but in practice it behaves much closer to a transition node — especially in terms of cost sensitivity, design discipline, and backend impact.
This article explains how 90nm wafer and MPW costs really work, and when
65nm represents a transition point in custom silicon. It is often the first node where cost, complexity, and risk start to rise meaningfully, while still remaining accessible for non–mega-scale ASIC projects.
Because of this, cost assumptions at 65nm are frequently wrong — especially when teams assume it behaves like
130nm sits at an important intersection between mature analog processes and more integration-friendly digital nodes. It is often chosen when designers need more density than 180nm, without the complexity of advanced nodes. Cost at 130nm is often misunderstood — especially when comparing MPW and full mask options.
This article explains
180nm remains one of the most widely used semiconductor process nodes for analog, mixed-signal, power, and industrial ICs. Despite its age, it is still a first-choice node for many new designs. Cost is often cited as the main reason — but understanding what actually drives 180nm wafer and MPW pricing
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Many teams talk about doing an ASIC long before they know whether an ASIC is actually feasible. In practice, ASIC feasibility is not a yes/no question.
It is a balance of economics, risk, schedule, and technical reality.
This article explains what really makes an ASIC project feasible —
Booking an MPW shuttle is often seen as a safe first step toward silicon. In reality, MPW only reduces mask cost risk — it does not protect you from an unready design.
Many MPW failures happen not because MPW is the wrong choice, but because the design was not
Multi-Project Wafer (MPW) runs are often described as a low-cost way to get first silicon. That’s true — but only if you understand what the MPW fee actually includes and, just as importantly, what it does not.
Many first-time teams underestimate MPW cost, not because MPW is expensive, but