Semiconductor Technology Node History and Roadmap

May 16, 2017, anysilicon

65nm, 28nm, 10nm, 7nm… If you follow Intel’s processors or Xilinx’s FPGAs, you have probably heard about the term semiconductor process node. Semiconductor foundries are investing billions of dollars to make the newest technology node available to the market.


Traditionally, the technology (process) node indicated to the transistor’s gate length. Today, things are more complex, therefore the technology node is basically a marketing name.


Here is an historical overview and roadmap for new technology nodes, showing an impressive and relentless development of new technology nodes in the last 30 years.



  • In 1997, most of the leading semiconductor introduced the 250nm process node.
  • The 180nm process node, was introduced in 1999 by most Intel, Texas Instruments, IBM, and TSMC.
  • Just 2 year later, Intel, Texas Instruments, IBM, and TSMC introduced the 130nm node.
  • The 90nm process node was introduced in 2004 by AMD, Infineon, Texas Instruments, IBM, and TSMC.
  • In 2006, Intel, AMD, IBM, UMC, Chartered and TSMC introduced the 65nm technology node.
  • Matsushita, Intel, AMD, IBM, Infineon, Samsung, SMIC and Chartered Semiconductor have introduced the 45nm process node.
  • The first 14 nm scale devices were shipped to consumers by Intel in 2014.
  • Samsung first released their version of a 10 nm process node in 2017.
  • In 2017, TSMC announced 7nm technology node production starting in 2018


(get the full size image here)

semicondctor technology node roadmap anysilicon small


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  • Bill Martin

    late seeing this post….process nodes have always been defined by minimum geometries that allowed an IC to work. If you go back in to the 1970-90s, this was the spacing between source/drain (or gate length). Shorter than this and a channel was not created and the S/D were shorted out. This controlled process migration for decades until foundries started to see a shift in what ‘minimum’ geometry caused failures. Typically today, it is all about metal spacing required to produce a working IC. Pitches less than the acceptable metal pitch causes high yield issues….So we have migrated from ‘gate length’ to ‘metal pitch’ and probably in the future it will be ‘atom’ width…..