80 results found
RTL Design, Design Verification, Physical Design, Analog Design
RISC-V Ultra-Low Power Core, Configurable Clock-Gated 32-bit Bus Manager
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Ring Based PLL’s, LC PLL’s, SerDes Interfaces, LVDS Interfaces, Free-Running Oscillators
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Custom RTL Design, Pre-Verified IP Cores, Verification & Validation
DDR & LPDDR Memory Controller IP, PCIe Controller IP, Ethernet MAC & PHY IP, AI/ML Compute Unit IP
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