Is TSMC going to smash Packaging Houses?

anysilicon May 8, 2013 No Comments

Two years ago TSMC announced its plans to expand into packaging services.  It is unclear how much these plans succeeded up till now, but it definitely seems that TSMC is now in an excellent position to take a big bite into the advanced packaging market, enter into direct competition with ASE, AMKOR, SPIL and STATSChipPac.

Why now?

how many bumps

We are recently hearing from many companies and semiconductor professional that 3D and wafer level package solutions are gaining popularity. The interest in high-end packaging is growing, as they resolve real problems.

The main driver behind 3D packaging technologies is enabling a higher level integration and faster data crunching for the networking market. Wafer level packaging is driven by the need to support the small size requirements of the mobile market. Both markets are growing, and TSMC seems to be have great chances in capturing these high-end segments.

Package types can be categorized along a continuum with small, low cost package solutions, like QFN package types on one end, and complex, expensive 3D packaging solutions on the other end. TSMC will compete on the expensive type of packages, which may better contribute to its revenue stream.

Since TSMC is handling wafer production, wafer level packaging is a natural extension. The line between wafer production and wafer bumping has become very thin, as can be seen in the screen capture below from TSMC’s site, offering several packaging services already.

Many customers will find it convenient having one company handle their wafer production and assembly services under one roof. Together with their testing services, TSMC will become a one stop shop for many new customers.

 

tsmc website

 

 

 

 

 

 

 

 

 

 

 

 

Packaging houses are obviously not thrilled with TSMC entry into their zone, as they will have difficulties competing with TSMC on technology and quality. Most assembly houses will probably compete on price and will be forced to lower their gross margin in order to win projects. Packaging houses may have to collaborate more closely with non-competing-foundries such as GLOBALFOUNDRIES, SMIC, SAMSUNG and others, who are not stepping (yet) on their toes.

 

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Foundry, Package
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What is a Burn-in Board?

anysilicon April 29, 2013 No Comments

Burn in Board is a printed circuit board which functions as a jig in the Burn-in process. The Burn-in Board is used as part of the ASIC reliability testing process during which components are stressed to detect failures. Burn in Boards consist of sockets to accommodate the tested ASICs and are designed to withstand the hot temperatures during tests.

 

burn in board image

Burn in Test

Burn in tests check the reliability of the ASIC device and are typically done at 125ºC, while electrical signals and power are applied to ASICs. Burn-in boards are inserted into the burn-in oven which supplies the necessary voltages to the samples while maintaining the oven temperature at 125ºC. After the stress testing the samples must be screened to ensure they passed the oven testing.

 

Burn in Board Materials

Burn in boards utilize high grade materials. For testing up to 125C a special version of FR4 is used (High Tg FR4). For higher temperatures up to 250C a Polyimide is used; and for very high temperatures up to 300C a High grade polyimide is used.

Burn in Board Design

In addition to the typical PCB design guidelines which are quite common among all PCB designers, there are a few additional factors for making a Burn in Board. One of the most important considerations is selecting the highest possible reliability and quality for the Burn in Board and the test socket. You don’t want your Burn in board to fail before the device under test. Therefore, all active/passive components and connectors should comply with high-temperature requirements, and all materials and components should meet high-temperature and aging requirements.

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Qualification
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Synopsys Mergers and Acquisitions History [infographic]

anysilicon April 17, 2013 No Comments

The following infographics shows Synopsys’s mergers and acquisitions along the years from its very beginning.

Synopsys was founded in 1986 by David Gregory, Aart de Geus and has been involved with many mergers and acquisitions. The very recent and large acquisitions are:

Year 2008

  • Synplicity
  • ChipIT

Year 2009

  • ChipIdea

Year 2010

  • VaST
  • CoWare
  • VirageLogic
  • Optical Research

Year 2011

  • Nsys
  • Extreme

Year 2012

  • Luminescent (Mask BU)
  • Magma
  • SprintSoft

synopsys acquisitions

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Chip Design
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Die Per Wafer Formula and (free) Calculators

anysilicon April 9, 2013 No Comments

Calculating the number of Dies Per Wafer (DPW) is a very simple and straight forward task. It’s actually based on basic high school mathematics which are related to circle area formula, remember Pi?

die-per-wafer

Silicon dies which are placed on a wafer can also be described as many squares placed inside a circle — thus the calculation is about first finding the overall circle area using both the mathematical number Pi (approximately equal to 3.14159) and the wafer size.

The wafer size and the die size are known in advance, however, as our “squares” have spaces between them (e.g. scribe lines) and the area located at the edge of the wafer cannot be used, the calculation is a bit tricky, therefore, some recommend using the Die Per Wafer tools results as an estimation rather than a calculation.

In addition to the above unused area, the foundry will use additional area for testing purposes (PCM structures) that will eat up relatively small size of the wafer. Sawing lanes, wafer margin and test structures size vary from process node to process node and from foundry to foundry. Therefore, is it highly recommended to have the final DPW figure directly from the foundry because they have all the knowledge and information required to provide the actual figure.

 

AnySilicon’s Die Per Wafer free Tool

Our free Die Per Wafer calculator is very simple and based on the following equation:

die per wafer formula

d – wafer diameter [mm] (click her for wafer size information)

S – die size [square mm]

For your convenient, we have placed the Die Per Wafer calculator as an online Excel sheet so you can use it online or download it into your ASIC price calculator.

Please refer to the following link: AnySilicon DPW Calculator

Other DPW calculators:

Two of my favorite on line DPW tools can be found here:

http://www.silicon-edge.co.uk/j/index.php?option=com_content&view=article&id=68

http://mrhackerott.org/semiconductor-informatics/informatics/toolz/DPWCalculator/Input.html

 

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Chip Design, Foundry, Full Turnkey
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Cadence Mergers and Acquisitions History [infographic]

anysilicon March 18, 2013 No Comments

The following infographics shows Cadence’s mergers and acquisitions along the years from its very beginning.

Cadence Design Systems was founded in 1988 by the merger of SDA Systems and ECAD and has been involved with 100 mergers and acquisitions. The very recent and large acquisitions are:

Year 2013

  • Tensilica
  • Cosmic Circuits

Year 2011

  • Azuro
  • Altos Design Automation

Year 2010

  • Denali

Year 2008

  • ChipEstimate

 

 

Cadence Acquisitions mergers

 

 

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Chip Design
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Understanding Process Corner (Corner Lots)

anysilicon March 11, 2013 No Comments

Process Lots (or corner lots) are special-modified-wafers that help verifying chip design robustness to accommodate process variations that statistically occur in wafer production over the years.

One of the products that semiconductor foundries offer is process lots (also called: corner lots, split lots or skewed lots). Corner lots wafers are a group of wafers which have been skewed by the fab to different corners.

The purpose of process lots is to help you find out whether your design will be immune to process variations in the future. A successful corner lot exercise includes production of process lots in all different corners. Thereafter these wafers need to pass the electrical test (by the ATE) at all corners.

corne_lot-wafer

The industry is using two-letter designation to describe the different corners, where the first letter refers to the NMOS device, and the second refers to the PMOS device.  There are 5 classic corners:

  • FF (fast fast)
  • SF (slow fast)
  • SS (slow slow)
  • FS (fast slow)
  • TT (typical typical)

The FF corner, for instance, is obtained by skewing both P and N devices to the fast corner. The TT corner is the center corner where wafers are normally produced (e.g. typical process parameters).

In typically chip project schedule, corner lots should be produced just after tapeout or before releasing to production.

Silicon foundries are also offering skewing of different parameters to see the effect of specific parameters on memory blocks for example. This will require deeper discussions with the process engineers to help identifying parameters in the process that can provide benefits.

 

 

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Foundry
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Who is Bigger and Stronger than TSMC?

anysilicon March 4, 2013 No Comments

I have the utmost respect for TSMC. For their advanced technology; for the quality of their products; for their ecosystem; and for their contribution to the industry. In fact, TSMC has become so big – that it will take a while until the second ranked foundry can catch up.

The deep sub-micron technology, particularly 28nm and below, has made the foundry business a game of investment, allocation and cash flow. Don’t get me wrong, the semiconductor business is still about technology innovation, but in today’s consumer market a shortage in 28nm wafer supply means less tablets and diminished phone production. Can the economy afford that?

Without a doubt, access to 28nm fabs has become a reason to fight for. 28nm process node introduced many advantages which are helping generate a competitive edge. Therefore, many components used in smartphones and tablets are based on 28nm technology, and tight access to the fab means securing the supply chain.

 

give me 28nm wafers

 

There are only a few giants that can build a new fab: Samsung, Intel, TSMC, GLOBALFOUNDRIES, ST and perhaps one or two more. So many end products and so few fabs. The fab is becoming extremely critical. But will it become the bottleneck?

In the meanwhile, a large company that changed its name from Apple Computers to just Apple is continuously accumulating capital and searching for a way to achieve a sustainable competitive edge.

Apple has been shopping for chip companies since 2008. They bought a memory company called Anobit in December 2011, acquired Intrinsity in April 2010, and P.A Semi in April 2008. If you wonder why Apple is buying chip companies it because they provide Apple an advantage and at the same time Apple blocks its competitors from accessing these wonderful technologies.

Apple is “eating” more of the supply chain, using its capital to buy chip technology and gain a competitive advantage.  With all the capital that Apple has in the bank, could the next step be the takeover of TSMC?

 

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Foundry
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A Simple Method for Choosing a Chip Design Company

anysilicon February 25, 2013 No Comments

In 2005 I applied for a job in Singapore. The job required some technical and business skills and therefore the interview was a bit tricky.

One part of the interview related to estimating market size. They asked me to estimate the number of Piano Tuning companies which are currently active in Tokyo, Paris and New Zealand. For the young readers, these are usually one-person company that tunes clients’ piano at their homes. Tuning is not required very often, maybe only every 1-2 years.

There are many things to consider here. First: culture. How popular is the Piano in those areas. Second: Finance. Can these people afford a Piano? Moreover, I know that houses in Japan are relatively small. Is there a place for a Piano in the house? I had just too many puzzles in my head and I only had 3 minutes.

Eventually I was wrong and did not get the job.

It would have been easier to find the answer if I was more familiar with the music industry or particularly with the Piano market. And it would have been a piece of cake, if I was a Piano tuning guy myself, right?

This brings me to a very interesting discussion around evaluating RFQ responses from ASIC design houses.

In some scenarios you may consider outsourcing your chip design activities to an external company.  Most of the fabless companies occasionally use external chip design teams because they lack internal resources.  The other type of companies, which are product companies, must use external services because their core competencies are not around semiconductors.

Like in my piano story, the question is how do you evaluate chip design contractors, which may be far away from your domain expertise? The answer is obviously the all-too-familiar RFQ.

chip design

 

While there are really many chip design companies out there, you should send out your RFQ or chip specifications to no more than 5 companies. Dealing with more than 5 vendors during the early exploration phase will consume too much energy and will slow you down.

You should look for a development team that brings great value and minimizes the project risk. A team which is ‘spot on’ your project requirements. One indication that I use, is comparing the schedules provided by the different design houses. Naturally, there will be a few companies with a very optimistic schedule and a few with a very pessimistic schedule.

Over the years I developed my own metrics. My rule of thumb is as follows: chip design companies that acquired relevant experience and can reuse some of the blocks from their previous projects will hand over the shortest schedule. And chip design companies which have no relevant experience will propose the longest schedule and thus also the highest risk.

In short, my recommendation is – look at the schedule and use it as an indicator to assess your risk.

Like in any other rule there are exceptions. If you are planning a very complex chip utilizing leading edge technologies it could easily take 5 years of development and 3 tape-outs iterations. But all in all, it’s very similar to my piano story -  it’s either guessing the way or knowing the way.

 

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Chip Design
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LeadFrame Overview and Custom-LeadFrame Benefits

anysilicon February 18, 2013 No Comments

The name leadframe (or lead-frame) is actually very accurate.

Leadframe is an alloy frame that consists of the package leads and the paddle. The silicon die is attached on the paddle and the leads are connected to the die with wirebonds. That’s it.

In the following photo you can see the paddle (center) which is typically used for ground signal and many leads around the package stretching from the package edge to a point where the wirebonder can reach.

 

leadframe

 

Many types of packages are based on leadframe, such as QFN, QFP, LQFP, TQFP, PLCC, SOIC and TSOP.

Like any other material, leadframe requires tooling. The tooling can either be open tools,which are available and can be used free of charge, or custom tools that are associate with an NRE cost.

Leadframes are produced in a long strip, which allows them to be quickly processed on assembly machines.

Open Tool LeadFrame

Packaging houses have many leadframes tooling on stock that can be available for your project. Therefore, it is wise to look around and ask several packaging houses whether they have open tools for your leadframe.  This will save you the NRE required for creating the tooling.

Custom LeadFrame

If open tools are not available then you’ll have no choice but to pay for a custom leadframe.

But, there are also some technical issues that may require the use of a custom leadframe:

For most application the length of the bond wire is not critical and there is no need to have a custom leadframe.

But for some designs, particularly RF applications, the length of the wirebonds may be vital. With a custom leadframe you can determine the distance between the die and the leads to achieve the exact wirebond length required.

In cases where the chip is too small for the selected package, a custom leadframe is needed to ensure the length of the wirebonds does not exceed the maximum length allowed by the package design rules.

 

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Package
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6 Ways to Improve Chip Yield Even Before the Project Starts

anysilicon February 11, 2013 No Comments

Early on in Chip projects, yield is not taken very seriously. The common thinking goes –  anyhow there isn’t much to do as this early point of time. However, there are actually several things you can do even before the Chip design starts, which will translate to clear savings.

Calculating Yield

1- Know your Yield

Yield has a great deal of impact only if production volume is high. If you plan to manufacture only a few tens of thousands of components, perhaps yield is not the most important topic in your project’s plan.

Yield can be roughly calculated or estimated before the project has even started. Yet, if you have calculate a yield target of 95% there is no reason to invest money and efforts to try improving the yield from (the calculated) 95% to 99% because that would not be possible.  Therefore, it is important that you have calculated your yield and set that as a goal.

2- Consider Foundry Applicability

Semiconductor foundries are not taking any yield losses. It is not the fab responsibility whether your yield is high or low because they sell wafers and not dies. Therefore you should select the foundry the suits best to your Chip domain.

If you chip requires small node geometries go to GLOBALFOUNDRIES, TSMC etc. If you chip needs excellent RF performance go to: IBM, TowerJazz etc. The foundry can help you calculating the wafer yield based on their own process technology. If you can provide them with die size, number of layers, process node and options, they should be able to provide you with a very accurate yield figures for your project.

3- Match Design Team Experience to Your Project

If you have decided to outsource the frond-end and physical design activities to an external vendor, the main yield-related risk here is experience. If the design team does not have the relevant experience that matches your chip project (for instance: RF, High Voltage) you are really wasting your time. Don’t hire analog designer without high voltage experience if you need to design a 120V chip.

4- Select Silicon Proven IPs

More and more companies are shopping for Semiconductor IPs to help reduce time to market and minimize engineering cost. There are many IP vendors with high quality products and some with lower quality. The keyword here is risk minimization. You really want to make sure the IP blocks you are about to purchase and integrate into your chip are bug free and have been silicon proven and qualified for your process. Ask for test results and references.

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5- Follow Package Design Rules

For simple QFN packages there are no real concerns besides following the assembly house design rules. However complex packages can reduce yield dramatically. If your chip uses a package that consists of a multilayer substrate with high speed signals, this substrate should be considered as part of the silicon die. Improper routing of high speed signals, for example, will make the substrate performance very marginal and thus result in failures during final test.

6 – Say No to Tight Test Limits, Say Yes to Better Hardware

The only place to measure yield is at the testing phase. And this is done by the ATE.

Great ASIC engineers often try to over-engineer the chip design and as a by-product also tighten up the test result criteria. These limits will have direct impact on your profit. Every device that fails to meet limits during the screening process will be scraped. Therefore, don’t create the perfect test specification. Make one that meets your system requirements.

Loadboards, sockets and probecards have different quality levels and therefore different cost. But since these are the actual physical interface between your chip and the tester, you want to make sure they have the right quality and durably to allow solid connectivity to the tester during the test period. Otherwise, lower quality hardware will shave off your yield figures. Sockets for example, have limited number of insertions; you therefore should buy a socket that meets your chip production volume. Bottom-line — don’t compromise on the quality of the hardware interfacing your chip.

 

There is so much more to write on this topic, we promise to write more articles in the future. Stay tuned.

 



												
																											

							

							
							
															

									

										

											
											
											

												
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