Staff ASIC Power Engineer, ML Accelerators

Join Google's AI and Infrastructure team as a key contributor to the future of AI/ML hardware acceleration. This role focuses on driving power efficiency for Tensor Processing Units (TPUs), essential for powering Google's most demanding AI applications. You will leverage your expertise in power design and optimization to develop innovative solutions that enhance the performance and efficiency of custom silicon technologies.

Responsibilities:

• Contribute to design power modeling and drive convergence to power targets.
• Investigate, spec, and deploy architectural and microarchitectural power optimization techniques.
• Define best practices and methodologies to achieve low-power RTL designs.
• Collaborate with cross-functional software and system teams to create novel power management architectures to meet dynamic power targets.
• Lead an experienced power team, owning the execution and delivery of complex technical projects end to end.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in design or architecture, including logic design, power architecture, performance, or SoC design.
• Experience with power design, modeling, architecture, or reduction methodologies.

Skills:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture (preferred).
• Experience defining and implementing chip-wide power management architectures and designs.
• Technical leadership and project ownership with a successful delivery track record.
• Understanding of modern power and thermal management techniques at silicon and system levels, including DVFS and Turboing.
• Ability to solve open-ended power and performance problems under ambiguity.