ASIC Design Engineer

Hewlett Packard Enterprise (HPE) is seeking an ASIC Design Engineer to join its Networking Silicon group, which specializes in advanced networking chips for routers and switches. This role is primarily onsite at an HPE office, emphasizing collaboration and innovation in a fast-paced environment. HPE values diverse backgrounds and offers opportunities for personal and professional growth.

Responsibilities:

• Develop detailed micro-architecture specifications from functional specifications that meet power and area requirements.
• Implement designs using Verilog or System Verilog.
• Write functional coverage and SystemVerilog Assertions (SVA) to assist in verification and catch corner case bugs.
• Collaborate with the Physical Design team for optimal floorplan and timing closure, identifying and fixing timing issues in RTL to meet frequency targets.
• Work with the Verification team to ensure full validation of design blocks.
• Mentor and guide new college graduates and interns to enhance leadership skills.

Qualifications:

• Bachelor’s degree in Electrical Engineering (Master’s preferred) with 3-4+ years of relevant experience.
• Strong analytical and problem-solving skills.
• Knowledge of computer architecture and networking protocols is a plus.
• Proficient coding skills in Verilog/System Verilog from coursework or prior experience.
• Familiarity with synthesis, lint, and other EDA tools is desired.

Skills:

• Excellent written and verbal communication skills.
• Knowledge of Perl/Python is a plus.
• Accountability and action planning.
• Active learning and listening skills.
• Agile methodology and Scrum development experience.
• Analytical thinking and creativity.
• Cross-functional teamwork and data analysis management.