ASIC/RTL Design Engineer

AMD is on a mission to create innovative products that enhance next-generation computing experiences across various sectors, including AI, data centers, PCs, and gaming. The company fosters a culture of collaboration and innovation, emphasizing the importance of diverse perspectives and teamwork. Joining AMD means being part of a forward-thinking environment that values execution excellence and bold ideas, ultimately shaping the future of technology.

Responsibilities:

• Contribute to the development of large SoCs with multiple physical blocks and complex timing constraints.
• Own and integrate RTL designs, ensuring quality and efficiency in SoC design processes.
• Develop and verify complex multi-mode/multi-corner timing constraints for RTL and signoff.
• Maintain and enhance RTL quality metrics in hierarchical designs, automating processes for efficiency.
• Implement pre-route timing checks and clean up QoR to ensure quality handoff for static timing analysis (STA).
• Collaborate with CAD teams on pre-production synthesis and STA workflows.
• Review and identify areas for process improvements and early issue detection during design phases.

Qualifications:

• Bachelor’s or Master's degree in Electrical Engineering or Computer Engineering.
• Extensive experience in SDC development and debugging.
• Hands-on experience with EDA tools for RTL quality checks and timing constraints.
• Experience in analyzing timing reports and resolving design-related issues.

Skills:

• Proficiency in EDA tools such as Synopsys Design Compiler and Primetime.
• Strong TCL scripting abilities in EDA environments and standalone Linux.
• Excellent written and verbal communication skills.
• Strong analytical and problem-solving skills.