ASIC/SOC DFT Engineer [Silicon Engineering]

SpaceX is seeking a motivated ASIC/SOC DFT Engineer to join its Silicon Engineering team, contributing to the development of next-generation ASICs for the Starlink broadband internet system. This role involves working with cross-disciplinary teams to enhance connectivity through innovative chip designs, ultimately supporting SpaceX's mission of enabling human life on Mars.

Responsibilities:

• Evaluate design readiness for scan insertion through RTL and physical design tools.
• Integrate and verify Design for Test (DFT) fabrics and IP within subsystems.
• Run and evaluate scan insertion through synthesis tools, refining recipes for maximum coverage.
• Conduct ATPG analysis to ensure quality scan chain construction and coverage goals.
• Run and debug non-timing and SDF annotated gate level simulations.
• Create ATPG content for post-silicon testing and validate through gate level simulation.
• Collaborate with circuit physical design, ATPG, and manufacturing teams to ensure high-quality scan coverage.

Qualifications:

• Bachelor's degree in electrical engineering, computer engineering, or computer science.
• 1+ years of professional experience working with ASICs.
• Experience in scan insertion or DFT setup.

Skills:

• Understanding of ASIC design flow, methodologies, physical design, and verification.
• Experience with high reliability design and implementations.
• Good scripting skills (csh/bash, Perl, Python, etc.).
• Familiarity with Verilog/SystemVerilog for design block implementation.
• Knowledge of UPF, formal verification, and DRC rule checking.
• Ability to adapt in a dynamic environment and work collaboratively in teams.