Senior ASIC Design Engineer, Google Cloud

Join Google's AI and Infrastructure team as a Design Engineer, where you'll shape the future of AI/ML hardware acceleration by driving the development of cutting-edge TPU technology. This role involves architecting and implementing SoC-level RTL for next-generation data center accelerators, collaborating closely with cross-functional teams to deliver high-performance silicon solutions.

Responsibilities:

• Drive the complete RTL life-cycle from initial microarchitecture to sign-off readiness for high-performance designs.
• Collaborate with system architects to align on chip-level bandwidth, latency, and power objectives.
• Partner with Verification and Physical Design teams to define test plans and achieve timing closure.
• Identify test requirements and execute testing of silicon systems, leading post-silicon bring-up to validate performance.
• Influence designs to enhance testing and debugging capabilities, establishing third-party IP requirements.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles and RTL design concepts.

Skills:

• Expertise in Verilog or SystemVerilog.
• Advanced RTL design skills with mastery of multi-clock domains and timing closure.
• Familiarity with ASIC flow, SerDes behavior, and scripting languages (Python, Tcl, or Perl).
• Knowledge of NoC/Memory architecture and performance tuning.
• Proven ability to lead cross-functional efforts with software and hardware teams.