Semiconductor Latest News

Moore’s Law Will Not Come To An End Anytime Soon

Gordon Moore said‚ on the 40th anniversary of his law that “Moore’s law is really about economics.” What did he really mean by that? In 1965 when Gordon Moore put forth Moore’s law based on his observation, those years were Golden years of Free Market Capitalism in America. The entire decade

Setup/hold interdependence in the pulsed latch (Spinner cell)

This is a guest post by Dolphin Integration which provides IP core, EDA tool and ASIC/SoC design service.
                                                                       

The IP Blame Game

This is a guest post by Methodics that delivers state-of-the-art semiconductor data management (DM)  for analog, digital and SoC  design  teams.

The topic of IP quality in the SoC era is difficult to define, and solutions to problems relating to IP quality, verification, and use are hard to find. Debates rage between IP users, suppliers,

TSV Integration is Creating Growth

“The long term growth of the equipment & materials business will be supported by the expansion of 3D TSV stack platforms” says Yole (Yole Développement) in its latest report, “Equipment & Materials for 3DIC & WLP Applications“. The market research and strategy consulting company, Yole proposes a deep analysis of the equipment &

The Macroeconimics of 450mm Wafers

SEMICON West 2014 in San Francisco was a great place to meet bloggers in the semiconductor industry to get updated on the status of 450mm diameter silicon wafers. On one side, there is a good news about the unprecedented level of collaboration taking place between the design and construction professionals

Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models

This paper describes the use of behavioral models and mixed-signal simulation as a means to verify the proper instantiation, connectivity and control of analog and mixed-signal (AMS) intellectual property (IP), and also as a means to prototype an AMS integrated circuit (IC) or system-on-chip (SOC) using behavioral models in place

What Does It Cost You When Your SoC is Late to Market?

If your chip is late to market, it is costing you far more than you know.
 
Arteris conducted a survey of all its chip design customers to gain a more accurate grasp of the major concerns they have in their day-to-day operations and to gain a better understanding of what

Low-Power VLSI Design Methodology

Low Power Design is the today’s need in VLSI. Why? Well, ask yourself ! You go to gadget shop, looking for a new cell-phone. Apart from the price, what are the qualitative things that you would be most concerned about?
 

Features including the speed of the processor
Battery back-up
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Selecting an embedded MCU for SoC

This is a guest post by Dolphin Integration which provides IP core, EDA tool and ASIC/SoC design services

 
When a SoC integrator has to select a microcontroller for his application, most of the time, he refers to his own previous experiences rather than on a rational assessment as no standard benchmarking

Flip Chip Market and Technology Trends

Yole Développement announces its Flip Chip Market and Technology Trends report. Yole Développement’s analysis updates the business status of the Flip-Chip market including data for TIM, underfills, substrates and Flip-Chip bonders. Discover fully updated 2010 – 2018 market forecast, detailed technology roadmap and bottom up approach, plus a strong focus