Get the semiconductor daily news directly to you by subscribing to our email list. For ASIC designer and managers, staying updated with the latest news, technologies, and trends is crucial. Here are the lastest news from the semiconductor industry.
Semiconductor Assembly and Test Services are converting rapidly into a pure outsourcing mode of operation. While today perhaps only 50% of the market is using Outsourced Semiconductor Assembly and Test (OSAT, or SATS) this number is set to increase in the future.
While many of the low-end suppliers are
QFN package is probably the most successful package type today. Offering low price, excellent performance and small size, it is an ideal package for many applications.
QFN (quad-flat no-leads) is a plastic SMT package consisting of: a leadframe, single or multiple dies, wirebonds and a molding compound. The
There are many ways to deliver, package and transport silicon products. Here’s a short primer that provides the basic facts regarding how silicon can be packed and delivered to ensure safe transportation with minimum damages.
There are two main options for receiving wafers from your foundry: tested or untested.
Read More
This post describes the growth of top 10 semiconductors companies in the last 10 years. It tracks the growth of the 10 semiconductor leaders from 2002 to 2011 and shares some nontraditional thoughts about the ten semiconductors vendors’ success:
Thought #1: Follow the market trends
Since the 80’s companies from USA,
We love copper (Cu) wire. In fact, we already described in our post “Copper Wire (Cu) Reduces Package Cost” the cost advantages of copper wire bonding compared to Gold (Au) wire. Copper wire introduced some challenges to assembly houses (such as ASE, Amkor, STATS ChipPAC) but also offers a few
Read More
Do you know someone that is not eager to reduce their ASIC production costs? I don’t. Some say that redesign changes can lead to significant cost reduction, for instance – using a more advanced silicon technology node to shrink the die size. True, but this is a really big, painful
Read More
Silicon wafers are the most essential element in the realization of ICs. The semiconductor industry had invested heavily to increase the wafer size during the last 30 years, so while foundries used to produce 1 inch wafers, today’s common wafer size is 300mm (11.8 times larger than 1 inch). There
Read More
BGA substrate design is a critical step in the development of many ASICs, SoCs, processors, sensors, RF devices and high pin-count integrated circuits. The package substrate acts as the electrical and mechanical bridge between the silicon die and the printed circuit board. It routes signals from the die pads or
Read More
Pure-play foundries are offering vanilla flavor services, meaning one can buy only wafers. ASIC design, testing, packaging and supply chain services are not part of their service offering.
Large IDM players, who manage their own supply chain, seek this type of engagement because they prefer to own the supply
Tapeout is a major milestone in every ASIC project lifecycle. It means the design phase is completed and you are ready to send out the GDSII to the fab for production.
The term “tapeout” was coined in 70’s. Historically, engineered used a magnetic tape to store all the ASIC design