Get the semiconductor daily news directly to you by subscribing to our email list. For ASIC designer and managers, staying updated with the latest news, technologies, and trends is crucial. Here are the lastest news from the semiconductor industry.
Developing a custom analog or mixed-signal ASIC requires specialized engineering expertise, the right semiconductor manufacturing process, and a carefully planned design and verification strategy. Whether the application involves sensor interfaces, power management, data conversion, medical electronics, or industrial control, choosing the right ASIC design partner is critical to achieving the
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In 2026, Pacific MicroCHIP marks 20 years of ASIC design services and turnkey solutions. We spoke with CTO Denis Zelenin about that journey, the company’s growing range of products—from a 56 GS/s ADC to RF spectrometers—and what customers increasingly expect from custom silicon.
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Choosing an Arm CPU core starts with the workload, not with the processor name. The right core depends on what the chip must do, the software it must run, the power and area available, whether deterministic real-time behavior is required, and how much performance the system actually needs. Arm offers
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An MPW run is one of the most cost-effective ways to manufacture first silicon when you do not yet need a full dedicated wafer lot. MPW stands for Multi-Project Wafer. Instead of one customer paying for the entire mask set and wafer fabrication process, multiple IC designs share
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TSMC MPW gives chip designers a lower-cost way to manufacture first silicon on TSMC technology without paying for an entire dedicated mask set and wafer run. TSMC operates its multi-project wafer program under the name CyberShuttle®. Several customer designs share the same multi-project mask set, which spreads tooling and wafer
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Advanced packaging has become the place where AI system performance is won or lost. High-end performance packaging revenue is forecast to grow to more than $51 billion in 2031, a 27% CAGR during 2025-2031, with package unit volume expanding at a 33% CAGR and wafer demand at 30%.
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IC prototype packaging is the bridge between first silicon and a device that engineers can actually handle, mount on a PCB and evaluate. For most prototype ASICs, sensors, mixed-signal ICs and MPW shuttle dies, the best approach is to use an existing package platform such as QFN, QFP, BGA or
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For semiconductor products entering production today, silicon remains the strongest choice when maximum routing density, proven HBM integration and the most demanding chiplet-to-chiplet bandwidth are required; organic or RDL interposers are usually more attractive when cost, large package size and mechanical compliance matter more than absolute interconnect density; and glass
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The practical difference is simple: 2.5D packaging places multiple dies side-by-side and connects them through a high-density interposer or bridge, while 3D packaging stacks dies vertically and connects them through TSVs, microbumps or hybrid bonding. In 2026, 2.5D remains the mainstream architecture for large AI accelerators, GPUs and HBM-based systems
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VQFN stands for Very Thin Quad Flat No-Lead, and it is best understood as a low-profile member of the QFN family rather than a fundamentally different package architecture. Like a standard QFN, a VQFN has no protruding gull-wing leads; the electrical terminals are located mainly on the bottom perimeter
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