80 results found
RTL Design, Design Verification, Physical Design, Analog Design
RISC-V Ultra-Low Power Core, Configurable Clock-Gated 32-bit Bus Manager
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SoC Verification, IP Level Verification, FPGA Prototyping, ASIC Implementation
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CC EAL5+ certification of customer chips, Secure personalization of customer chips
TESIC RISC-V CC EAL5+ Secure Element, TESIC CC EAL5+ Secure Element
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Turnkey ASIC – Full-Cycle Silicon Development, RTL Design & Verification, Analog Mixed-Signal Design and Layout, Synthesis, DFT & Physical Design, Post-Silicon Validation, IP Services, Product Engineering Services
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Design Services, Foundry Access, Custom IP, Turnkey Solution, makeChip Hosted Design Service Platform
0.4V Standard Cell Library for 22FDX (22nm FDSOI), Adaptive Body Bias Solution for 22FDX (22nm FDSOI)
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