Die vs. bin? Lot vs. device?

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    As a software developer; I will need to work/develop app according to exist Semiconductor database. I am still new in Semiconductor field; While I know what is the Lot, wafer and the die. I still need to know what is the bin?! How is it related to die? Why Lot is joined with device? How is it known devices related to Lot?
    Is there any documentation about this?
    I really need your help, any comment or link will be highly appreciated.
    (I did many search on google but didn’t find what I need, maybe I am not good on search or there lack of info about these)


    Bin is a number that is referenced to a test that fails during production test.
    Each test in the production test flow is linked to either soft(ware) bin (usually used in wafer map that shows the result of each die and which test it failed) or hard(ware) bin (usually defines the tray which the failed chip was placed in to differentiate it from the passing chips).


    It can be very tricky to actually understand the details. You can get an idea by watching youtube videos such as: https://www.youtube.com/watch?v=yKl71IX8Zc0

    Before calculation define you supply chain, then you can define the parameters for each phase and thereafter the calculation becomes easy.

    The sorting is either on wafer level or device level depending upon the cost-trade-of between wafer cost/die size, yields and packaging cost.
    The sorting is in principle two classes (bins): pass or fail. But in praxis you also have “continuety” and special parameter sets that enables to track trends.

    In many cases you also have more pass bins – that can be to sort out high and low perfomance dies or devices.


    I found this, which could help someone like me in the future :
    A wafermap (generated after test the wafer) categorizes the passing and non-passing dies by making use of bins. A bin is then defined as a good or bad die. This wafermap is then sent to the die attachment process which then only picks up the passing circuits by selecting the bin number of good dies. The process where no ink dot is used to mark the bad dies is named substrate mapping. When ink dots are used, vision systems on subsequent die handling equipment can disqualify the die by recognizing the ink dot.


    Wafer test:
    The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. For example, thin film metrology based on ellipsometry or reflectometry is used to tightly control the thickness of gate oxide, as well as the thickness, refractive index and extinction coefficient of photoresist and other coatings. Wafer test metrology equipment is used to verify that the wafers haven’t been damaged by previous processing steps up until testing; if too many dies on one wafer have failed, the entire wafer is scrapped to avoid the costs of further processing. Virtual metrology has been used to predict wafer properties based on statistical methods without performing the physical measurement itself.[1]

    Device test:
    Main article: Wafer testing
    Once the front-end process has been completed, the semiconductor devices are subjected to a variety of electrical tests to determine if they function properly. The proportion of devices on the wafer found to perform properly is referred to as the yield. Manufacturers are typically secretive about their yields, but it can be as low as 30%. Process variation is one among many reasons for low yield.[2]

    The fab tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. Currently, electronic dye marking is possible if wafer test data is logged into a central computer database and chips are “binned” (i.e. sorted into virtual bins) according to the predetermined test limits. The resulting binning data can be graphed, or logged, on a wafer map to trace manufacturing defects and mark bad chips. This map can also be used during wafer assembly and packaging.

    Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as the “final test”.

    Usually, the fab charges for testing time, with prices in the order of cents per second. Testing times vary from a few milliseconds to a couple of seconds, and the test software is optimized for reduced testing time. Multiple chip (multi-site) testing is also possible, because many testers have the resources to perform most or all of the tests in parallel.

    Chips are often designed with “testability features” such as scan chains or a “built-in self-test” to speed testing, and reduce testing costs. In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during the testing, in order to achieve tightly-distributed resistance values as specified by the design.

    Good designs try to test and statistically manage corners (extremes of silicon behavior caused by a high operating temperature combined with the extremes of fab processing steps). Most designs cope with at least 64 corners.



    For clarification of some the topics addressed above:

    Bin: a bin is a grouping of a test the simple form is pass vs. fail, but also continuity are used. Subclasses of pass bins is often used. It can be on sensitivity, speed or other parameters. Bin classes can both be SW bins and HW bins.

    Ink of wafers. IT is an old technology which is seldom used today. Electronic wafer maps is preferred.

    Wafer maps: Wafer maps is not only provided at electronic test, it is often also inspection maps e.g. bump inspection maps or exclusion maps. Those maps is merged together to give a test map or a P&P map.


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