can someone please explain the warpage phenomena? why it is happening? what type of packages are likely to suffer from it? how to avoid it? thanks!
our assembly partner recommend to use copper pillar for our product. What is the difference between CP and regular bumps? is this recommended for new products? Best -- Steffen
We are designing an IC that has mems inside in addition to our .13u IC. Can we test the mems on a regular ATE (94K or J750)?
we have an option to buy an IP from a large IP provider and from a small one, there is a HUGE price difference and both IP are silicon proven, what am ...
What is the best job interview for ASIC designers in your own view?
my company would like to start a chip project. is it true that making a digital chip will be lower cost than analog one?
Can anybody help to explain how a temperature sensor inside a chip works? Best regards, PP
Hello, what type of quality inspections fabs perform before they ship out wafers? BR, Raul
Who is the leading CPU IP core provider after ARM (I know that ARM is #1)?
hi everyone, I enjoy this site very mush. One quick question. How do one come around estimating yield for calculating chip price? the project is 0.13, 8.4mmsq fully digital. What assumption should one make? with ...
can I please get your opinion on what should be (or what is the required) wafer thikness for QFN package and BGA package? Thanks! JJ
I am just wondering, Intel is the biggest and most powerful semiconductor company in the world, with many decades of experience, why did they fail to sell a chip to the mobile ...
Hello, I am new to this forum. Can anyone help with this question? What is the max number of pins (IOs) for a QFN package? Best, Debra
My company has never designed ASICs, but now it looks like we have a real project that will be designed as a chip (IC). When we talk to vendor they brag about ...
Hello ALL, we are planning a wafer sort test for our digital chip in 40mn, there is an internal debate on what is the very first thing to test after touchdown, please ...
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