When someone talk about hard bumps, what does it mean? I have heard its better to utilize hard bumps for wafer sort, can someone elaborate, please? EMO
Is FIB an operation that takes a few days or a few hours? BR Mariana
and what is it used for?
As a software developer; I will need to work/develop app according to exist Semiconductor database. I am still new in Semiconductor field; While I know what is the Lot, wafer and the ...
I know it sounds a bit crazy but we are using today a wafer scale package, is there any way to get the package size smaller than WLCSP? Thank you in advance, Giovani.
I would like to know if it i better to run tests on ATE load board when socket is connected directly to the board or via receptacle? does it matter? is there any ...
we are planning to design a chip for IoT, this will be the 1st design for our company, what tip can you share to help us keep our ASIC design cost low? Thanks ...
dear all, we are a small IP core company in Europe with a few interesting IPs that we believe could be ideal to Broadcom. Can you share some of your selling experience in ...
Dear sir, I need some more clarification regarding GDSII files. the following are the questions which i have in my mind 1.Can we create our own libraries and adding them to ...
i'm a nanothecnology student from Sapienza, Rome, Italy. I have to create a varactor, more exactly an RF-MEMS for an exam. I would like to know how much costs a nitride encapsulation ...
I've been using FPGA for 3 year , why designing a custom chip is so costly? are they any cost that I don't foresee? BigMike
GloFo are very proudly the biggest semiconductor private company, is this a big deal? what is the advantage of being a big private company? SeekingAlpha
Is the number of ASIC design companies (world-wide) increasing or decreasing? is there any consolidation in this market?
we are running big ASIC projects in high volume and having an internal debate, perhaps one of you could share his experience and thoughts, would you recommend producing corner wafers (split lot), ...
we have been told that every wafer we produce has PCM DATA structures. Can anyone please explain what it is, and what can we learn from these DATA?
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