MILPITAS, Calif. — April 29, 2026 — The SEMI Silicon Manufacturers Group (SMG) reported today, in its quarterly analysis of the silicon wafer industry, that worldwide silicon wafer shipments increased 13.1% year-on-year to 3,275 million square inches (MSI) from the 2,896 MSI recorded during the same quarter of 2025. Sequentially, shipments declined 4.7% quarter-over-quarter from the 3,437 MSI
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TES Electronic Solutions GmbH announces the availability of the Configurable Display Controller (CDC) IP core family, a scalable and modular solution designed to support a wide range of embedded display applications. The CDC enables developers to efficiently manage video- and image-composition, blending, and output in systems ranging from FPGA-based platforms to application-specific ASICs.
The
Woodcliff Lake, NJ — April 27, 2026 — CAST, a leading provider of semiconductor intellectual property cores, today announced the MAC-SEC-MG MACsec Protocol Engine IP core, extending the company’s secure Ethernet IP offerings with a multi-gigabit MACsec engine optimized for providing 10G+ Ethernet in ASIC and FPGA designs requiring secure channels.
The new MAC-SEC-MG core
TES Electronic Solutions GmbH offers an Integer-N Phase-Locked Loop (PLL) IP designed for high-frequency clock generation and frequency synthesis in on-chip applications. Built on X-FAB XT018-0.18µm BCD-on-SOI CMOS technology, this integrated PLL features an integrated loop filter, a high-performance VCO, and robust stability, making it ideal for applications demanding precise timing, low jitter, and long-term
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AMD’s upcoming MI500 may matter for more than just GPU performance. The bigger story is co-packaged optics and what it could mean for the future of AI infrastructure. If MI500 moves in that direction, it would signal that the next phase of AI competition is no longer only about faster accelerators. It is about connecting
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The strongest takeaway from TSMC’s 2026 North America Technology Symposium is that the old model of simple node-to-node progression is fading. In its place, TSMC is building a roadmap that separates cost-efficient scaling from performance infrastructure, with some technologies aimed at smooth migration and others designed to solve the physical constraints of AI and HPC.