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Challenges in Measuring Theta jc for High Thermal Performance Packages

This is a guest post by Jesse Galloway and Ted Okpe of Amkor Technology. Article reprinted from May 2014 Electronics Cooling magazine.

One of the more challenging thermal resistance measurements to make for electronic packages is the junction-to-case resistance called Theta jc. The equation for Theta jc, equation (1), is straightforward.

Can you reduce cost and development cycle of your next ASIC?

Have you ever wondered about the possibility of minimizing risk, design time and production cost simply by working with different IC design or verification companies? Or whether you could make your current ASIC cheaper by changing your FAT (foundry, assembly, test) providers?
 
Actually it’s something you can do right

Don’t Get Critical IP Cores from a ‘Supermarket’

This is a guest post by PLDA which designs and sells intellectual property (IP) cores and prototyping tools for ASIC and FPGA

You are on a tight schedule for your next chip. Not wanting to reinvent the wheel, you plan to go to an outside vendor for some of your silicon

ASIC Design Flow – an Overview

Today, ASIC design flow is a very solid and mature process. The overall ASIC design flow and the various steps within the ASIC design flow have proven to be both practical and robust in multi-millions ASIC designs until now.
 
Each and every step of the ASIC design flow has

How to make THE difference in SoC power management architecture

This is a guest post by Dolphin Integration which provides IP core, EDA tool and ASIC/SoC design services

 
To reduce the Bill-of-Material (BoM) and to simplify their usage, System-on-Chips (SoC) become more and more complex due to the integration of a large number of features previously located on board. This increase

Choosing IP core – It’s not just the product, it’s the relationship

This is a guest post by PLDA which designs and sells intellectual property (IP) cores and prototyping tools for ASIC and FPGA

You are on a very strict schedule for your next chip. Not wanting to reinvent the wheel, you plan to go to an outside vendor for some of your

Overview and Dynamics of Scan Chain Testing

This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India.

In accordance with the Moore’s Law, the number of transistors on integrated circuits doubles after every two years. While such high packing densities allow more functionality to be incorporated on

Will more ASIC design companies cooperate with Apple and Google?

It’s no secret that Google, Amazon and Apple are heavily involved in the semiconductor industry. Apple itself is the biggest buyer of chips and estimated to buy 10% of chips sold worldwide.  Google uses Intel’s CPUs in their server farms and represent alone 4% of Intel total sales.
 
Both

My Golden Rule for Chip Production Testing

Chip production testing is probably the most underestimated task by ASIC development engineers. And yet, testing is an essential step with a direct impact on final chip cost.
 
Let’s start with the basics. Testing of chips is necessary because the chip manufacturing process cannot provide 100% yield. Silicon foundries

Submitting design files to Assembly house – a Checklist

While assembly houses are gradually becoming more and more organized in regards to following internal processes, it seems that we, their customers, are often trying to push them to make shortcuts only because “we are running out of time”.
 
With chip design cycle time shrinking, production related tasks such