Chip IP

IP Cores

DisplayPort 1.4a Transmitter, DisplayPort 1.4a Receiver, Display Stream Compression (DSC 1.2a) Encoder, Display Stream Compression (DSC 1.2a) Decoder

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Services

Physical Design, RTL Synthesis and verification, STA

IP Cores

DDR

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Services

SoC Verification, IP Level Verification, FPGA Prototyping, ASIC Implementation

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Services

IP Customization, Low power, small footprint Design Methodology, Integration Services on Customer FPGA Boards, System Design, Consulting

IP Cores

IEEE 802 Data Center and Wireless FEC , OpenZR+/ Open ROADM oFEC 800GbE, SDA, ITU High-Speed Optical Communication IP Cores, Full ETSI DVB-S2X Wideband Transmitter and Receiver, AWGN Channel, 3GPP Mobile Communications

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