80 results found
Logic Design (Front-End), ASIC Design RTL to GDS2, Analog & RF Design, Productization, Production, Additional Services
CPU & SoC, Security, General Purpose IP, Analog IP
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IP Provider for unique I/O and ESD protection, Custom I/O and ESD Design
Low Voltage ESD/EOS protection (up to 5V), HV/BCD EOS/ESD protection (5V and higher), LIN PHY (transceiver) , Programmable Clipping Circuit for Antenna pins, Radiation hard circuits, IP for chiplet Die-2-Die interfaces
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Custom RISC-V Core Development, RISC-V SoC Subsystem Development
Azurite: 32-Bit RISC-V Processor, ARM M-0 to M-4 Equivalent, PPA Optimised, Calcite: 32/64-Bit RISC-V Processor, ARM A-35 Equivalent, PPA Optimised
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RTL Design and Verification, Design Verification, Design For Test, Physical Design, Static Timing Analysis, Post Silicon Validation
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