80 results found
ASIC Design, Embedded Algorithms Design, Wafer Testing, Packaging , Quality
High-Voltage IP Cores, Analog IP Cores , Digital IP Cores
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RTL Design, Design Verification, Physical Design, Analog Design
RISC-V Ultra-Low Power Core, Configurable Clock-Gated 32-bit Bus Manager
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Intellectual Property (IP) & Process Technology, SoC/ASIC Development Platform, Design Flow, Packaging & Testing, Production Service, Application-Oriented Value-Added Services
USB3.1 Gen1 IP Solutions, Technology Optimized Standard Cell Library, ESD Robust Multi-Voltage I/O, Low Power SRAM with High Production Yield
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IP Provider for unique I/O and ESD protection, Custom I/O and ESD Design
Low Voltage ESD/EOS protection (up to 5V), HV/BCD EOS/ESD protection (5V and higher), LIN PHY (transceiver) , Programmable Clipping Circuit for Antenna pins, Radiation hard circuits, IP for chiplet Die-2-Die interfaces
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