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RTL Design, Verification, Analog Layout, Physical Design, System Engineering, Embedded Software/Firmware
Custom SerDes, ARM HSSTP PHY with Link Layer, PCIe PHY, XAUI PHY, CEI SR PHY, SATA PHY
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Design Verification, Design Implementation (RTL to GDSII), RTL Design, Design for Test (DFT), Analog & Mixed Signal Design, Emulation and Post Silicon Validation
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Analog / Mixed Signal ASIC Design, Circuit Design, Back-End Services, Custom PDK and PCELL, Low Cost ASIC or ASSP, Smart Integrated Power
Analog Signal Path IP (Amplifiers, ADCs, DACs, LDOs)
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SoC Verification, IP Level Verification, FPGA Prototyping, ASIC Implementation
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