Are Power Planes Necessary for High Speed Signaling?

April 23, 2015, anysilicon

The performance of a system depends heavily on the communication speed between integrated circuits, which is constrained by the power delivery networks (PDNs). The disruption between the power and ground planes based on the low target impedance concept induces return path discontinuities during data transitions, which create displacement  current  sources  between  the  power  and  ground  planes.  These  sources induce excessive power supply noise which can only be reduced by increasing the capacitance requirements through new technologies such as thin dielectrics, embedded capacitance, high frequency decoupling capacitors and other methods. The new PDN design proposed here using power transmission lines (PTLs) enables both power and signal transmission lines to be referenced to the same ground plane so that a continuous current path can be formed. Extensive simulations and measurements are shown using the PTL approach to demonstrate the enhanced signal integrity as compared to the currently practiced approaches.


1. Introduction

A power delivery network (PDN) is the network that connects the power supply to the power/ground terminals of the ICs. In conventional design of PDNs, the PDN impedance is required to be less than the target impedance over the frequency range of interest to minimize the IR drop and to suppress the inductive noise during data transitions. As a result, most PDNs in high-speed systems consist of power and ground planes to provide a low-impedance path between the voltage regulator module (VRM) and the integrated circuit (IC) on the printed circuit board (PCB), as shown in Figure 1.

Figure 1: Power distribution network using power and ground planes.
Recently, on-board chip-to-chip communication is being pushed from several Gbps towards tens of Gbps due to the demand for higher data rate [1]. Single-ended signaling is widely used for memory interface, but it suffers from simultaneous switching noise (SSN), crosstalk, and reference voltage noise [2]. Although differential signaling is free from common-mode noise, it doubles on-chip interconnect count, off-chip printed circuit board (PCB) trace count, and I/O pin count [3], which results in higher cost. To achieve better signal integrity with less expense, studies on pseudo-differential signaling schemes have been undertaken by several researchers [3]-[8]. The original pseudo-differential signaling adds a reference line after a group of data lines, usually limited to four, which results in N+1 physical lines routed in parallel to communicate N signals. Afterward, further improved versions of pseudo-differential signaling schemes have been proposed, which  are  bus  inversion  scheme  [4],  incremental  signaling  scheme  [3][5],  balanced coding scheme [6]-[8], and so on.
These signaling schemes still have a limitation in terms of noise reduction due to the PDN. For off-chip signaling, charging and discharging signal transmission lines induce return currents on the power and ground planes [9], as shown in Figure 2. The return current always follows the path of least impedance on the reference plane closest to the signal transmission line. The return current path plays a critical role in maintaining the signal integrity of the bits propagating on the signal transmission lines. The problem is that the disruption between the power and ground planes induces return path discontinuities (RPDs), which create displacement current sources between the power and ground planes. The current sources excite the plane cavity and cause voltage fluctuations. These fluctuations are proportional to the plane impedance since the current is drawn through the PDN by the driver. Therefore, low PDN impedance is required for power supply noise reduction, which can only be achieved by increasing the capacitance requirements through new technologies such as thin dielectrics, embedded capacitance, high frequency decoupling capacitors, and others [10]-[14]. In addition, use of power and ground planes as part of the target impedance concept is making the packages and boards more complex, leading to the need for sophisticated design tools and methodologies. So, the  question  to  be  asked  is:  Are  power  (voltage)  planes  necessary  for  high  speed signaling?  Instead,  can  an  alternate  method  be  developed  based  on  a  high  target impedance concept that provides a more stable signaling environment with less complexity  in   terms   of   the   design   tools   and   methodologies   required?   This   is accomplished in this paper by using power transmission lines.





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This is a guest post by Suzanne L. Huh and Madhavan Swaminathan which is the  Founder of E-System Design.

  • Bill Martin

    Profs. Swaminathan and Han wrote a book “Design and Modeling of 3D ICs and Interposers” that also discusses some future architectures being explored for Power Distribution Networks.
    The rest of the book is a fascinating discussion of new techniques to accurately and quickly analyze any via (TSV, TGV, etc) that can be applied at chip, package and PCB designs.