May 24, 2015, anysilicon
The flip-flops in a design which are fed by the same clock signal or by any clock which is synchronous to a master clock constitute one clock domain. The term clock domain is often used interchangeably with clock groups. These clock domains are of a particular interest while performing timing analysis of a design because all the interactions within a clock domain needs to be checked for any potential setup and hold time violations and need to fix before the tape-out. On the other hand, any interaction between the clock domains need to be explicitly checked for synchronizers and they can then be treated as false paths.
It is desirable to have stringent clock skew margins for all the interacting flops within a clock domain to facilitate timing closure.