Clock Latency

January 21, 2015, anysilicon

Clock Latency is the general term for the delay that the clock signal takes between any two points. It can be from source (PLL) to the sink pin (Clock Pin) of registers or between any two intermediate points. Note that it is a general term and you need to know the context before making any guess about what is exactly meant when someone mentions clock latency.

Clock Latency is the total delay that a clock signal takes to reach a sink or a destination pin, which typically is the clock pin of the flip-flops or the latches, from a clock source. Source maybe output of the Phase-Locked Loop (PLL) or perhaps from the output of a clock divider.

Clock latency is an important parameter in timing. In ideal scenario, it is required to have the clock latency to be the minimum. However, in modern SoCs the clock paths are typically long where the clock needs to be routed from the source located on one side of the chip to the destination pic of a flop located on the opposite side.