May 24, 2015, anysilicon
The minimum amount of time after the active clock edge till which the input data must remain stable so that the data at the next flop is captured in the same clock cycle is referred to as hold time.
Like setup time, hold time is also a characteristic of flip-flops and is modeled in the timing libraries as a function of input slew at the data pin and the slew at clock pin. Hold checks are typically done at best PVT conditions, taking into account the best case delays and best case slews. Unlike setup time violations which may be fixed by lowering the clock frequency, hold time violations are independent of the clock frequency and therefore are of greater concern to the designers. Negative clock skew and slower data-paths may facilitate hold timing closure.