February 25, 2013, anysilicon
In 2005 I applied for a job in Singapore. The job required some technical and business skills and therefore the interview was a bit tricky.
One part of the interview related to estimating market size. They asked me to estimate the number of Piano Tuning companies which are currently active in Tokyo, Paris and New Zealand. For the young readers, these are usually one-person company that tunes clients’ piano at their homes. Tuning is not required very often, maybe only every 1-2 years.
There are many things to consider here. First: culture. How popular is the Piano in those areas. Second: Finance. Can these people afford a Piano? Moreover, I know that houses in Japan are relatively small. Is there a place for a Piano in the house? I had just too many puzzles in my head and I only had 3 minutes.
Eventually I was wrong and did not get the job.
It would have been easier to find the answer if I was more familiar with the music industry or particularly with the Piano market. And it would have been a piece of cake, if I was a Piano tuning guy myself, right?
This brings me to a very interesting discussion around evaluating RFQ responses from ASIC design services.
In some scenarios you may consider outsourcing your ASIC design activities to an external company. Most of the fabless companies occasionally use external ASIC design services because they lack internal resources. The other type of companies, which are product companies, must use external services because their core competencies are not around semiconductors.
Like in my piano story, the question is how do you evaluate ASIC design companies, which may be far away from your domain expertise? The answer is obviously the all-too-familiar RFQ.
While there are really many ASIC design companies out there, you should send out your RFQ or chip specifications to no more than 5 companies. Dealing with more than 5 vendors during the early exploration phase will consume too much energy and will slow you down.
You should look for a development team that brings great value and minimizes the project risk. A team which is ‘spot on’ your project requirements. One indication that I use, is comparing the schedules provided by the different design houses. Naturally, there will be a few companies with a very optimistic schedule and a few with a very pessimistic schedule.
Over the years I developed my own metrics. My rule of thumb is as follows: ASIC design companies that acquired relevant experience and can reuse some of the blocks from their previous projects will hand over the shortest schedule. And chip design companies which have no relevant experience will propose the longest schedule and thus also the highest risk.
In short, my recommendation is – look at the schedule and use it as an indicator to assess your risk.
Like in any other rule there are exceptions. If you are planning a very complex chip utilizing leading edge technologies it could easily take 5 years of development and 3 tape-outs iterations. But all in all, it’s very similar to my piano story – it’s either guessing the way or knowing the way.