Category Archives: Packaging
IC Packages Price Calculator
IC Package Price calculator is an online IC package price estimation tool that covers all the major IC package types exist today.
To use the IC package price tool simply select the IC package type, number of pins and volume and the tool will send you an email with
Qualcomm Opens Semiconductor Test Manufacturing Site in Shanghai
Qualcomm Incorporated (NASDAQ:QCOM) today announced the opening of Qualcomm Communication Technologies (Shanghai) Co. Ltd., a semiconductor test facility in the Waigaoqiao (WGQ) free-trade zone in Shanghai, and its first foray into providing manufacturing services for semiconductors. By working with Amkor Technology, Inc., one of the world’s leading providers of contract
Read MoreInvestment: Wafer Level Packaging Company Receives $51.5M Investment
Deca Technologies, a wafer level packaging provider to the semiconductor industry, announced today the receipt of an additional $51.5 million investment from a leading electronics company. Combined with the previously announced investment from ASE of $60 million, and following the repurchase of $20.6 million of shares held by Cypress Semiconductor Corp.,
Read MoreQFN Package Body Size and Lead Count – Infographics
QFN package is the most successful package type today. Offering low price, excellent performance and small size, it is an ideal package for many applications.
QFN package comes in different size and different lead count. This infographics shows the most popular body size and lead count provided by leading OSAT
AnySilicon Launches Online Package Price Estimation Tool
AnySilicon, the fastest-growing semiconductor vendors platform has announced today the availability of its free Semiconductor Package Price Estimator which provides package price for all major semiconductor packaging type.
Using this free tool, companies can get quick price estimation for the packaging and assembly prices which are becoming critical in many
2.5D & 3D ICs — Do We Have A Liftoff?
All the work that’s been done on stacked die really could pay off soon.
The challenges of Moore’s law scaling at advanced technology nodes are well documented. I won’t repeat them here. The benefits of “more than Moore” scaling (i.e., 2.5D and 3D ICs) are also well-known. This technology
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