Category Archives: Packaging

Understanding Wafer Bumping Packaging Technology

wafer bumping feature

Consumer electronics markets, the mobile phone market in particular, are extremely demanding. They are driven by the desire to pack more and more functionality and enhanced value into the same size handheld device, and often at lower costs. This drive towards smaller, cheaper and thinner consumer electronics has driven the

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IMI global and Beckermus Cooperation

Partnership

We are happy to announce that Beckermus and IMI has signed a strategic cooperation agreement. The cooperation goals are focused on enhancing each party advantages and facilities to support clients’ needs.
 
In a nutshell, Beckermus will supply Integrated Micro-Electronics Inc. (IMI) with prototype assembly services for microelectronics, micro-optics, photonics and electro-optics and

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Amkor Factories Receive Key Automotive Certification

car

Amkor Technology, Inc., a leading provider of semiconductor packaging and test services, today announced that multiple factories have passed certification audits for IATF-16949:2016, a key certification required for manufacturers who supply products to the automotive market. IATF-16949:2016 replaces and supersedes the older ISO/TS-16949 standard.


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OSAT Companies Ranking 2016-2017

Old CPU chips and obsolete computer processors

Despite the common belief, OSAT (Outsourced Semiconductor Assembly and Test) companies are very innovative. Many look at TSMC or Synopsys and consider their R&D work as innovative. But actually, semiconductor assembly industry is as innovative as any other company in the industry. We just don’t hear about it.
 
Semiconductor

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ASE and Cadence Deliver First System-in-Package EDA Solution Tailored for ASE’s High-Performance, Advanced IC Package Technologies

text labeled PRESS RELEASE

Advanced Semiconductor Engineering, Inc. (ASE, TAIEX: 2311, NYSE: ASX), and Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced they have collaborated to release a System-in-Package (SiP) EDA solution that addresses the challenges of designing and verifying Fan-Out Chip-on-Substrate (FOCoS) multi-die packages. The solution consists of the SiP-id™ (System-in-Package – intelligent

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Accurate Performance Analysis Requires Package Modeling

qfn

System performance is a critical requirement for the vast majority of integrated circuits that are designed today. To meet these stringent performance requirements, IC designers invest considerable time and effort in accurately modeling and simulating chip level performance – all to avoid nasty surprises when the first chips return from fabrication. Performance

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