Understanding ESD HBM in IC Design

In building integrated circuits (ICs) or ASICs, one area of concern is how they are protected from outside electrical sources. While most systems are geared towards power overloads, one source that may cause considerable damage is the electro-static discharge (ESD) that comes from the human body. To help test for ESD in VLSI, the standard i the use of the Human Body Model (HBM).

What is the Human Body Model (HBM) ESD?

The HBM ESD is the model used to characterize the susceptibility of ASIC/VLSI/semiconductors that might be subject to damage from ESD. In the US, there is a military standard of HBM used called MIL-STD-883, Method 3015.9 which is now common across all testing for ESD. This national standard makes it simpler for testing to be performed and provides a singular model so that all devices can be judged on their resistance to ESD. There is another standard used internationally called JEDEC JS-0001.

ESD HBM

How HBM ESD Model Works?

Under both national and international standards, the HBM ESD test is represented by a 100 pF capacitor combined with a 1500 ohm discharge resistance. Under the test, several kilo-volts are charged into the capacitor which usually include the following levels:

2 kV
4 kV
6 kV
8 kV

Then, the electricity is discharged through the resistor which is connected into the series of the IC itself and the results are observed. The ESD HBM provides a standard from which the ESD can be measured and the results seen so that any necessary changes can be made to the IC for additional protection.