Is Charge Sharing Silently Killing your ASIC Design?

October 01, 2016, anysilicon

Sharing is caring, unless it is as vital as required charge to function your ASIC design. As we move down from 20nm and below on designs with low voltages, charge sharing is quickly becoming mission critical problem in high performance custom ASIC designs using dynamic logic. Moderate charge sharing may slow down your circuits, while excessive charge sharing may cause functional failure.

In this article, we introduce charge sharing problem, discuss ill effects thereof, and suggest alternates to reduce the effects.



Little About Dynamic Logic


Dynamic logic is up to twice as fast compared to static CMOS and therefore presents itself as a preferred option for high performance custom circuits. An example of dynamic NAND gate is shown in Figure 1. These gates operate with clock  (CLK) signal’s precharge and evaluate cycles. Precharge cycle pulls output to logic one and evaluate cycle evaluates input states.



What is Charge Sharing?


Given capacitors (C2 and C3 in figure 1) on internal nodes are discharged in previous evaluate cycle, output charge (C1 in figure 1) brought by logic-1 during precharge cycle will be shared with internal node C2 in the following evaluate cycle when input B set to zero.


Example of Dynamic Logic Charge Sharing

Figure 1: Charge Sharing Example in Dynamic NAND gate.



This charge sharing may cause output voltage drop and further cause unintentional switch of receivers resulting in functional failure of the chip. Example of 10% voltage drop in NAND gate with 14nm Predictive Technology Model from ASU with high performance models ptm14hp is shown in Figure 2.


Charge Sharing Signal Voltage Drop of a NAND gate at 14nm

Figure 2: Charge Sharing induced Voltage Drop in 14nm NAND gate.



How to Avoid Charge Sharing


Paripath product inCharge analyzes design for charge sharing violations. Paripath inCharge will identify and report violating nodes using ultra-fast and accurate static analysis technology. Once these nodes are identified, employ one of the following techniques to remove violation


  1. Add a secondary precharge PMOS to every other NMOS in evaluation stack. However, it increases chip area and adds to complexity.
  2. Artificially increase load on output. However, it slows down circuits and may add crosstalk.
  3. Increase parallelism of evaluation stack. But It adds area and complexity of the chip.




In this article, we introduced dynamic logic and charge sharing problem associated with them. Later sections were used to explain and demonstrate 10% voltage drop in a 2 input NAND gate at 14nm.



This a guest post by Paripath, find more information here: http://www.paripath.com/

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