Layout/PD

5049611

21 yrs EDA / ASIC Methodology and PD / STA / UPF professional.

3511351

India

I have been working as Layout engineer . I also have experience in drc, lvs and latchup deck writing.

06061970

Ireland

A highly experienced Physical Designer with over 20 years of knowledge gained in the Semiconductor Industry, providing both CMOS and BiCMOS mixed signal layout design services.

7250019

USA

ASIC/SoC physical design engineer and project manager with 20 years of industry experience. Expert in all steps required to go from RTL to GDSII.

5049601

USA

Highly experienced and skilled physical design engineer with vast experience with tools and process nodes.

20221031

Netherlands

High-level proficiency in interpretation of Calibre / PVS / Assura DRC, LVS and ERC. Strong background in layout design considerations (Matching, Latch-up, ESD, Electromigration, Charge-up, Antenna Effect) to ensure the quality of work.

0012562

Canada

Electrical Engineer with76 years of experience with strong scripting skills in various scripting languages. I am highly motivated to learn about electronics including ASIC and PCB design, hardware acceleration and AI chips.

1357911

Armenia

Synthesis, timing analysis, place and route, PV, python, tcl, shell, Synopsys: DC, FC, PT, ICV