Find here a list of ASIC consultants in verification design, verification design IC consultants, ASIC verification design freelancers, ASIC verification design contractors, verification circuit design consultant, semiconductor verification design consultants and asics verification design electronics consultant.
India
I have been working as Layout engineer . I also have experience in drc, lvs and latchup deck writing.
Israel
30 years of experience in: SystemVerilog & UVM, Verilog, VHDL & Chip Design Expert & Lecturer.
USA
ASIC/SoC physical design engineer and project manager with 20 years of industry experience. Expert in all steps required to go from RTL to GDSII.
USA
A problem-solving and self-motivated ENGINEERING EXECUTIVE with demonstrated experience in electrical engineering, semiconductor processing, design of experiments, testing, electrical and physical failure analysis for root cause.
Romania
I am a senior verification engineer, working in ASIC functional verification since 2005. I have deep knowledge on ASIC verification using SystemVerilog with UVM and e language (Specman) with eRM.
USA
I am Verification Engineer, with Hands on expertise on ASIC/IP/Subsystem Verification, also excelled in VIP development, Very much optimistic and ready to learn new things.
Belgium
A motivated and dedicated digital IC design engineer with 9 years of experience. Experienced in digital frontend design flow, from initial conception through design and verification to signoff activities like Static Timing Analysis.
Armenia
Synthesis, timing analysis, place and route, PV, python, tcl, shell, Synopsys: DC, FC, PT, ICV
USA
Experienced Semiconductor professional from Amazon, Intel, Cadence, Qualcomm, and Texas Instruments specialized in CAD/EDA Flow Development, Automation and Programming to setup new flows or maintain/enhance existing design methodologies.
Philippines
Seasoned Analog/Mixed Signal IC designer providing consulting services and technical write-ups for each stage of the LSI development flow, including EDA and process automation.