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High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect stacked DRAM die. In its first implementation, it is being integrated with a system-on-chip (SoC) logic die using 2.5D silicon interposer technology.
In June 2015, AMD introduced its Fiji
Later this month, IC Insights will release its new 2016 IC Market Drivers Report. The report contains analyses on automotive electronics, the Internet of Things, tablet PCs, smartphones, medical and health systems, and several other mature and emerging electronic systems.
The upcoming IC Market Drivers Report finds that from 2014 through 2019, the
Israeli start-up Glassify joined the IoT revolution and introduces the first beer glass integrating a semiconductor chip. The beer glass allows consumers to connect the glass to the smartphone using NFC technology.
According to the company the new beer glass allows consumer to enjoy a more personal
SK hynix, Inc., Amkor Technology, eSilicon, Northwest Logic and Avery Design Systems have joined forces to offer a complete high-bandwidth memory (HBM) supply chain solution. HBM is a JEDEC-defined standard that utilizes 2.5D technology to interconnect an SoC and an HBM memory stack. Many companies are already using HBM to
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Samsung Electronics, the world leader in advanced memory technology, announced today that it has begun mass producing the industry’s first 10-nanometer (nm) class* , 8-gigabit (Gb) DDR4 (double-data-rate-4) DRAM chips and the modules derived from them. DDR4 is quickly becoming the most widely produced memory for personal computers and IT
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Nothing is permanent except change and need constantly guides innovation. Taking a holistic view with reference to a theme throws light on the evolution of the subject. In a pursuit to double the transistors periodically, the design representation has experienced a shift from transistors à gates à RTL and now to synthesizable models. As
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TSMC, the world’s largest pure-play semiconductor foundry, plans to build a 12“ wafer fab a service center in Nanjing, China.
The new facility in China would be able to produce up to 20,000 12” wafers per month and will start production of 16-nanometer process technology in 2018, according to
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its digital, signoff and custom/analog tools have achieved V1.0 Design Rule Manual (DRM) and SPICE certification from TSMC for its 10-nanometer (nm) FinFET process. Cadence and TSMC are also continuing to collaborate on the advancement of 7nm technologies and have completed
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Iddq testing is one of the many ways to test CMOS integrated circuits in production. These circuits are usually tested as a way to find different types of manufacturing faults. Electric faults can be a major hazard and it can even lead to fatalities. This method relies on measuring the
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The NVM Express (NVMe) specification has been introduced in 2011. Five years later, it is definitely adopted as the new standard storage interface for Solid-State Drives (SSD). Even if SAS and SATA SSDs are still dominating the market (in unit shipment), the PCIe SSD market share is growing fast and
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