Semiconductor Latest News

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INTEGRA TECHNOLOGIES EXPANDS SILICON PHOTONICS CAPABILITIES

Silicon Valley, CA (Feb 9, 2021) – Integra Technologies, a world leader in semiconductor packaging, assembly, test, characterization and related services, today announced the successful implementation of a high accuracy fiber array waveguide attachment system focused on the Silicon Photonics market. This latest set of tools is based on the double-sided HexNano

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CEO Talk: Doug Myron of Criteria Labs

This interview was held with Douglas Myron, President & CEO of Criteria Labs
 

 
Tell me a bit about your background? How did you first get started with Criteria Labs?
 
Well, I joined the team at Criteria Labs in 2005 as President and CEO after spending more

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SCALINX, Semiconductor Fabless Focusing on Signal Conversion Chips Secures 10.5 Million Euros Funding

Paris, France, February 3, 2021– SCALINX, a fabless semiconductor company specialized in advanced signal conversion chips, today announced it has secured global financing of 10.5 million euros. The investment validates recent progress and will enable SCALINX to meet growing market demand, drive the technology into new markets, increase capacity to

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Renesas to adopt Crypto Quantique’s QuarkLink security platform as part of its microcontroller ecosystem for the IoT

LONDON, February 8th, 2021 – Crypto Quantique, a specialist in quantum-driven cybersecurity for the internet of things (IoT), is collaborating with Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, to add its universal IoT security platform, QuarkLink, to the Renesas secure microcontroller ecosystem. QuarkLink supports devices that use

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Chipus Increases Online Exposure with AnySilicon

news

AnySilicon, the leading marketplace for ASIC service providers, announced today that Chipus, a semiconductor company focused on the development of mixed-signal ASICs, intellectual property (IP) blocks and IC design services, has joined AnySilicon to promote its IC design services and IP blocks. As part of the AnySilicon platform, Chipus will

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The Ultimate Guide to Clock Gating

Clock Gating is defined as: “Clock gating is a technique/methodology to turn off the clock to certain parts of the digital design when not needed”.
 
The Need for Clock Gating
 
With most of the SoCs heavily constrained by power budgets, it is of utmost importance to reduce power

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2020 Global Silicon Revenue Remains Stable as Wafer Area Shipments Edge Up Despite COVID-19 Disruption

market research

ILPITAS, Calif., Feb. 2, 2021 /PRNewswire/ — Worldwide silicon wafer area shipments in 2020 increased while revenue remained unchanged from 2019 at $11,170 million, the SEMI Silicon Manufacturers Group (SMG) reported in its year-end analysis of the silicon wafer industry. Silicon shipments totaled 12,407 million square inches (MSI), compared to 11,810 MSI shipped in

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AnalogX Announces World’s Lowest Power SERDES IP in 7nm and 6nm and Expansion Plan

AnalogX, the leading provider of multi-standard connectivity SerDes IP solutions, today announces the availability of its silicon-proven 7nm & 6nm SERDES. AnalogX is the market leader in low-power SERDES IP, serving the chiplet and chip-interconnect market with 16nm, 12nm, and now 7 nm & 6 nm technology nodes. The company also

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HDL Design House Partners with Marketing Platform AnySilicon

news

AnySilicon, the leading marketplace for ASIC service providers, announced today that HDL Design House, a leading-edge digital, analog, and back-end design and verification services provider, has joined AnySilicon to promote its design services. As part of the AnySilicon platform, HDL Design House will gain access to a full range of

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Webinar – High End Electronics meets Optics

AEMtec GmbH located in Berlin Germany provides a new 2021 Eight Session Webinar Series “Next Level of Technology – High End Electronics meets Optics”. Launch of webinar series in February. New industry trends, technology portfolio, implementation strategies as well as already successfully generated applications will be shown. The participant receives the

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