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PLL IP Core

March 25, 2019, anysilicon

A Phase Locked Loop, also known as a PLL, is an electronic circuit that receives an input signal and utilizes an oscillator to generate an output signal that has the same phase as the input signal.  A PLL detected the difference between the phase or frequency of two different signals and uses it to adjust the phase of the signal it transmits. In ASIC/SoC application, a PLL is used used to generate a clock and distribute it.

 

Generally, a Phase Locked Loop consists of a circuit having a variable frequency voltage-controlled oscillator for the generation of a signal, and a phase detector which keeps comparing the phase of the generated periodic signal to the input periodic signal so that it can make the necessary adjustments to ensure that both of them match each other in terms of phase and frequency. The clock signal that is produced by the oscillator is considered to be the output signal of the circuit. Another component called the loop filter is responsible for filtering out the output signal from the reference and the input signals. As such, it is the control center for the stability of the loop and the speed of the lock.

 

For their function, PLLs are used widely across a multitude of fields and applications. One of its most important functions is synchronization and demodulation, making it a widely used technology in telecommunications and radio. They are also frequently used for deskewing and clock multiplying purposes, as well as for clock recovery. Not only that, but they can also be used to generate a clock and distribute it.

 

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