I understood that each wafer comprises of process control monitor (PCM) data 1. What is it exactly? 2. Why is it important to me as a customer? 3. How much space is it taking on ...
Hello! One must wonder after seeing that ARM is taking over INTEL CPU market, what will be the IP or technology that will risk ARM domination? in other word, if ARM is ...
Dear all members of this forum, Maybe it's a big question, but what in your opinion makes TSMC so successful? there is such a huge gap between TSMC and the other fabs....
what would you recommend for a low volume wafer probe technology? cantilever or vertical? or anything else in the market?
for a FC BGA package, with a high speed power hungry chip, what are the top 3 methods to solve IR drop issue?
Hello guy! Which IP companies are considered today as leaders in the area NV memories IP? Is it Cadence? or Synp? Thanks! Rafael.
what is the typical price adder to an automotive qualified wafer, I have heard it's 20 percent increase to a "regular" wafer. Is this correct?
for performing ESD testing (according to jedec), should all pins be zapped?
Howdy semiconductor folk, Would you be so kind to explain that different: Short Loop and Daisy Chain Why are they needed / used. thanks a bunch, Koji
can someone please explain the warpage phenomena? why it is happening? what type of packages are likely to suffer from it? how to avoid it? thanks!
our assembly partner recommend to use copper pillar for our product. What is the difference between CP and regular bumps? is this recommended for new products? Best -- Steffen
We are designing an IC that has mems inside in addition to our .13u IC. Can we test the mems on a regular ATE (94K or J750)?
we have an option to buy an IP from a large IP provider and from a small one, there is a HUGE price difference and both IP are silicon proven, what am ...
What is the best job interview for ASIC designers in your own view?
my company would like to start a chip project. is it true that making a digital chip will be lower cost than analog one?