Category Archives: IP Cores

Talking Sense with Moortec – ‘From Moore’s Law to Moortec’s Law!’

No-one likes being put on the spot and yet we all like a forecast…and as we all know, the only guarantee with a forecast is that it is wrong. Sports commentators have carved out a special niche for themselves with the ‘commentators curse’, just as they extol the virtues of

Secure-IC is ready for ASIL B or ASIL D levels projects with its Securyzr integrated Secure Element

The Automotive industry is undergoing a revolution. Electrification of vehicles and autonomous driving are pushing forward an already big demand on embedded electronics for the automotive industry. This technological boom translates into more electronic devices into the cars, replacing a multiplicity of functions by their electronics counterpart.
 
This tendency

CAST and Fraunhofer IPMS Introduce CAN XL Bus Controller IP Core

Woodcliff Lake, NJ — September 8, 2020 — Silicon intellectual property provider CAST, Inc. and developer Fraunhofer IPMS today announced a new option for their popular CAN 2.0 and CAN FD Controller IP Core that adds support for the evolving CAN XL standard.
 
CAN XL is a new data

CEO Talk: Murilo Pilon Pessatti of Chipus Microelectronics

This interview was held with: Murilo Pilon Pessatti, CEO of Chipus Microelectronics.
 

 
 
Tell me a bit about your background? How did you first get started with Chipus?
I am an Electrical Engineer with a MSEE in Analog IC design. I studied in Brazil at São Paulo

Sofics releases Analog I/O’s and ESD clamps for TSMC N5 process

Belgium, August 24, 2020 – Sofics bvba (www.sofics.com), a leading semiconductor integrated circuit IP provider announced that its TakeCharge® Electrostatic Discharge (ESD) portfolio is silicon proven on TSMC’s advanced 5nm process technology. More than 100 fabless companies use Sofics solutions to enable higher performance, higher robustness while reducing design time

DDR IP Hardening – Overview & Advanced Tips

What is DDR?
 
As the name says Double Data Rate, DDR is the class of memory which transfers data on both the rising and falling edge of clock signal to double data rate without increase in frequency of clock. It uses PLLs (Phase Locked Loops) & self-calibration to reach