80 results found
RTL Design, Design Verification, Physical Design, Analog Design
RISC-V Ultra-Low Power Core, Configurable Clock-Gated 32-bit Bus Manager
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1G to 1,000Gbps Interlaken IP cores, 1G to 400Gbps Ethernet IP Cores, Low latency Ethernet for Financial Markets
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CC EAL5+ certification of customer chips, Secure personalization of customer chips
TESIC RISC-V CC EAL5+ Secure Element, TESIC CC EAL5+ Secure Element
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Advanced ASIC Development, New Product Introduction (NPI) Engineering, High Volume Manufacturing (HVM) Enablement
HBM3 PHY & Controller, Non-Coherent Network-on-Chip (NOC), Coherent Network-on-Chip (NOC), DDR5/4 PHY & Controller, Die-to-Die (D2D) Interconnect, Analog & Configurable I/Os
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Logic Design (Front-End), ASIC Design RTL to GDS2, Analog & RF Design, Productization, Production, Additional Services
CPU & SoC, Security, General Purpose IP, Analog IP
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