AN JOSE, Calif., Feb. 28, 2024 — QuickLogic Corporation (NASDAQ: QUIK), a leading developer of embedded FPGA (eFPGA) IP and User Tools, ruggedized FPGAs, and Endpoint AI/ML solutions, is proud to announce its selection by a top-tier Defense Industrial Base company for eFPGA IP targeting the GlobalFoundries’ 12LP, 12nm low-power process.
Read MoreFebruary 26, 2024 — Noesis Technologies has announced today the immediate availability of its ntFFT_UHS IP Core that implements a customized FFT/IFFT programmable fixed point (Decimation in Frequency – DIF) transform processor, supporting low latency, streaming, ultra-parallel complex samples per clock cycle in natural order. Input, internal and output 2’s complement
Read MoreLONDON, Feb. 14, 2024 — Reduced Instruction Set Computing (RISC)-V processor architectures are starting to address edge Artificial Intelligence (AI) workloads, and this trend is set to continue throughout the decade. According to a new report from global technology intelligence firm ABI Research, while RISC-V’s penetration into AI workloads is only just beginning,
Read MorePortland OR – February 6, 2024 — Trilinear Technologies, a leading provider of cutting-edge technologies for display connectivity and semiconductor solutions, is proud to announce its strategic collaboration with key industry partners to support the integration of VESA’s DisplayPort Automotive Extensions (DP AE) into automotive systems. This initiative reflects Trilinear’s commitment
Read MoreMILPITAS, CALIFORNIA, UNITED STATES, February 2, 2024 — SignatureIP, the pioneer of next generation NoC tools, has launched its new iNoCulator™ NoC configuration tool with a free trial period of two weeks for customers. The NoC (Network on Chip) is the backbone of a chip that provides the interconnect infrastructure between
Read MoreSANTA CLARA, Calif. – January 31, 2024 – Eliyan Corporation, credited for the invention of the semiconductor industry’s highest-performance and most efficient chiplet interconnect, today announced the successful tape out of the industry’s highest performing PHY solution for multi-die architectures, achieving bandwidth of 64Gbps/bump on a 3nm process using standard packaging. The
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