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Electrical Failure Analysis (EFA) of Integrated Circuits

When an integrated circuit fails, one of the first questions is: How is the device failing electrically?   A chip may exhibit excessive leakage current, a short circuit, an open connection, abnormal supply current, a parametric shift or a complete functional failure. Before engineers physically cut into the device, they usually want to ...

Nanoprobing for Semiconductor Failure Analysis

Nanoprobing is an advanced electrical characterization and fault-localization technique used in semiconductor failure analysis to directly investigate individual transistors, contacts, vias and interconnect structures inside an integrated circuit. Instead of relying only on package-level electrical measurements, nanoprobing allows extremely small conductive structures on a deprocessed semiconductor die to be contacted using ...

Creonic Adds oFEC Codec IP Core to Portfolio, Expanding High-Speed Networking Solutions for ASIC and FPGA

Kaiserslautern, Germany – May 21, 2025 – Creonic GmbH, a leading provider of ready-to-use IP cores for ASIC and FPGA applications, announces the release of its new oFEC (Open Forward Error Correction) codec IP core. The solution supports next-generation optical and high-speed communication systems and is now available in both ...

IC Decapsulation: Methods, Process and Applications

Many semiconductor failure-analysis techniques require direct access to structures that are hidden inside an IC package. The semiconductor die, bond pads, bond wires and other critical components may be completely covered by epoxy molding compound or other packaging materials. Before these structures can be examined using techniques such as optical microscopy, emission ...

PHIX Photonics Assembly

The Netherlands

Packaging foundry aiming to become world leader in the assembly of photonic ICs in scalable volumes.

Package Failure Analysis Services | IC Package FA Lab

Package failure analysis is the systematic investigation of defects and failures originating within semiconductor packaging, interconnects, solder connections, die attach, bond wires, redistribution layers and other structures that connect the semiconductor die to the outside system. A semiconductor device may fail electrical testing even though the silicon itself is functioning correctly. ...

Understanding Wafer Cost

The factors affecting silicon wafer cost are numerous. From the resistivity required for different applications to the physical size of the wafers, and not least the quality grades that separate the pristine from the less perfect; each aspect intricately influences the cost.     As we embark on this explanation, we'll unwrap the ...

Introduction to Silicon-Germanium (SiGe) Technology

Overview of Silicon-Germanium (SiGe) Technology and Historical Development   Shockley's early transistor game most likely inspired the notion of fusing silicon (Si) and germanium (Ge) to create an alloy for use in transistor engineering. However, this concept has just become a reality in the last 15 years due to the challenges associated ...

BCD, CMOS, FinFET, SOI, GaN & SiC Technologies Explained

Introduction to Semiconductor Semiconductors have a small energy gap between the conduction and valance bands, and their conductivity is between insulators and conductors. At absolute zero temperature, semiconductor materials are pure insulators and gradually increase with temperature. Temperature and doping are the two mechanisms to manage the conductivity of semiconductors. Doping ...

ficonTEC and PHIX partner to enable high-volume manufacturing of multi-chip photonic modules

PHIX B.V. of Enschede, The Netherlands, is a Dutch packaging foundry that assembles their customers’ photonic integrated circuits into complete modules. As these modules evolve from initial prototypes into mature products, the manufacturing volumes become much larger and a higher level of automation is required. This aspect of photonic device ...