The richest directory of IC Design House worldwide. Find the IC Design House that matches your needs.
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ASIC Design , Testing and Packaging, Qualification and Failure Analysis, Supply Chain Management, IoT Operations Outsourcing Solutions, RF and Mixed-Signal Test, Front-end Tape-out, Mask and Wafer Procurement, Back-end Manufacturing and Test, GLOBALFOUNDRIES Channel Partner
RFID analog front-end
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RTL Logic Design, Functional Verification, Place and Route / Layout, Architecture Design, FPGA Prototyping and Emulation, Leadership and Consulting: Technology Selection, Methodology, Planning, Audits
Custom IP Core or VIP Development
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ASIC Design, ASIC Production, ASIC Production Management, Replacement of Obsolete Components
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Custom IC Solutions, Design and Supply of Industrial ASICs , Design and Supply of Automotive ASICs
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Turnkey ASIC / SOC Development, Technology Development Platform, Technology Development Platform, Analog Circuit Design, Integrated Circuit Layout, Digital Design (RTL Design) and Verification, Digital Physical Design
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RTL2GDS2, Functional Verification, Frontend Design, Backend Design, Embedded Systems Design
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Design Services, Time and Material (T&M) contracting
PRBS-71532-HS: 32Gbps Pseudo Random Bit Sequence (PRBS) Generator/Checker of 7, 15, 31 order., 32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter, 32Gbps, 31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter, 32Gbps, 7/15 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
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Design Service, Layout Implementation and Verification Service, Pre-Silicon Validation Service, ASIC Testing Service
Low-Power Low-PhaseNoise VCO 1.5-1.9 GHz
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ADVANCED VERIFICATION, ASIC/FPGA/HW, EMBEDDED SYSTEMS AND SOFTWARE DESIGN, FUNCTIONAL SAFETY, TRAINING, EIC ACADEMY
TRNG IP Cores, SHA3 IP Cores, RSA Keygen IP Cores, RSA IP Cores, ECDSA IP Cores, DRBG IP Cores, AES GCM IP Cores, MIL-STD-1553-IP CORE, ARINC664 END SYSTEM IP CORE, ARINC664 SWITCH IP CORE, ARINC429 IP CORE, PRACH IP Suite
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Smart Integrated Power, Wireless Communications, RF-Energy, Characterization and Testing, EDA, Consultancy and Training Services, Supply Chain Management, Certifications
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IP Customization, Low power, small footprint Design Methodology, Integration Services on Customer FPGA Boards, System Design, Consulting
IEEE 802 Data Center and Wireless FEC , OpenZR+/ Open ROADM oFEC 800GbE, SDA, ITU High-Speed Optical Communication IP Cores, Full ETSI DVB-S2X Wideband Transmitter and Receiver, AWGN Channel, 3GPP Mobile Communications
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SystematIC- Custom ASIC Design, Turnkey (Supply chain Services), Sensor Interfacing, Integrated Power, High Voltage Expertise
Analog IP
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Integrated Circuit (IC) Design, Full Turn-Key ASIC Supplier, Fabless Manufacturing
Logic Families, Analog
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Custom RTL Design, Pre-Verified IP Cores, Verification & Validation
DDR & LPDDR Memory Controller IP, PCIe Controller IP, Ethernet MAC & PHY IP, AI/ML Compute Unit IP
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Intellectual Property (IP) & Process Technology, SoC/ASIC Development Platform, Design Flow, Packaging & Testing, Production Service, Application-Oriented Value-Added Services
USB3.1 Gen1 IP Solutions, Technology Optimized Standard Cell Library, ESD Robust Multi-Voltage I/O, Low Power SRAM with High Production Yield
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ASIC, SOC design, Foundry services, Turn key (supply chain management), Package and testing , TSMC’s official VCA (Value Chain Aggregator) , MPW and mini ASIC Services
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ASIC Design, Analog / Mixed Signal ASIC Design, RF ASIC & IP Design, Turn-Key Design & Supply Chain Management, IP Development / Verification / Characterization
Pipeline ADC, SAR ADC, RFID Building Blocks, Voltage Regulator
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IP Provider for unique I/O and ESD protection, Custom I/O and ESD Design
Low Voltage ESD/EOS protection (up to 5V), HV/BCD EOS/ESD protection (5V and higher), LIN PHY (transceiver) , Programmable Clipping Circuit for Antenna pins, Radiation hard circuits, IP for chiplet Die-2-Die interfaces
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ASIC Design, Embedded Algorithms Design, Wafer Testing, Packaging , Quality
High-Voltage IP Cores, Analog IP Cores , Digital IP Cores
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