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Electrical Failure Analysis (EFA) of Integrated Circuits

When an integrated circuit fails, one of the first questions is: How is the device failing electrically?   A chip may exhibit excessive leakage current, a short circuit, an open connection, abnormal supply current, a parametric shift or a complete functional failure. Before engineers physically cut into the device, they usually want to ...

PHIX Photonics Assembly

The Netherlands

Packaging foundry aiming to become world leader in the assembly of photonic ICs in scalable volumes.

Faraday Unveils ASIC Success in Factory Automation

Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today announced that it has won and delivered several factory automation (FA) related ASIC projects, supporting real-time Ethernet, EtherCAT, Profibus, and PLC controllers. In each case, Faraday employs its value-added ASIC and IP customization service for power-performance ...

FIB Circuit Edit

What is a Circuit Edit?   A circuit edit is when you need to modify an existing ASIC or integrated circuit for whatever reason. This is usually done with the help of an ion beam that is focused onto the chip to modify it as per the request of the designer. Engineers ...

IC Failure Analysis Techniques: A Complete Guide

When an integrated circuit fails, identifying the damaged component is only part of the challenge. Engineers must determine where the failure occurred, what physical or electrical mechanism caused it, and ultimately why it happened. This requires a combination of specialized IC failure analysis techniques. Some techniques detect electrical abnormalities without physically altering ...

Physical Failure Analysis (PFA) of Semiconductor Devices

Once an electrical failure has been localized inside an integrated circuit, the next challenge is determining what physically went wrong.  Was a metal interconnect broken?  Did a via fail?  Is there contamination between two structures? Has a dielectric layer broken down? Is a transistor structure abnormal? Or did the failure originate in the ...

Creonic Adds oFEC Codec IP Core to Portfolio, Expanding High-Speed Networking Solutions for ASIC and FPGA

Kaiserslautern, Germany – May 21, 2025 – Creonic GmbH, a leading provider of ready-to-use IP cores for ASIC and FPGA applications, announces the release of its new oFEC (Open Forward Error Correction) codec IP core. The solution supports next-generation optical and high-speed communication systems and is now available in both ...

Silicon Photonics Inflection Point - It’s Not ‘If,’ It’s ‘When’

Lately, there’s been a lot of buzz about silicon photonics in the data center industry. What’s it all about? The ever-expanding digital universe is being driven by cloud computing, mobile data, video streaming, and Internet-of-Things (IoT). Today, it’s estimated that by end of 2016, more than 6 zettabytes (i.e., the ...

Why Dr. Morris Chang is not My Hero. A tribute to Failure Analysis Engineers

  Dr. Morris Chang is not my hero. He might be the most important person in the semiconductor industry in our lifetime, but he is not my hero. I have nothing against him. I’ve never met him and probably will never will. Instead, I meet my heroes usually after tape-out, when ...

Comparing Au, Pt, Ag and Cu Wire Bonding

With the creeping rise in the price of gold, many microelectronics manufacturing companies have been looking for alternatives to reduce the cost of ball bonding. Recently, the trend has been to look into the use copper wire. However, there are many drawbacks to using copper wire, including the short shelf ...