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Semiconductor Failure Analysis Process: From Failure to Root Cause

When a semiconductor device fails, the visible damage is not necessarily the root cause. A damaged metal line, cracked package, leaking transistor or burned bond wire may be the final result of a sequence of events rather than the original problem. The purpose of the semiconductor failure analysis process is therefore to ...

RoodMicrotec

Germany

RoodMicrotec provides SCM, Test, Qualification, Failure Analysis and Engineering services to automotive, aerospace, industrial, consumer, medical markets and fabless companies.

The 6 Must-Do’s for Semiconductor Fabless Start-ups

Getting funding for a semiconductor startup is not getting easier. According to CBIngishts, there have been fewer than 20 Angel/Seed and Series A deals in the USA in each year since 2009.   So where is all the funding channeled to? In 2013, close to a quarter of all VC funding was ...

Common IC Failure Mechanisms and Their Causes

Integrated circuits can fail for many different reasons. Some failures originate inside the semiconductor die, while others result from packaging, manufacturing, assembly, electrical overstress or the environment in which the device operates. Common IC failure mechanisms include electrostatic discharge (ESD), electrical overstress (EOS), electromigration, dielectric breakdown, interconnect defects, corrosion, contamination, thermal ...

OBIRCH for Semiconductor Failure Analysis: Resistive Fault Localization

OBIRCH (Optical Beam Induced Resistance Change) is a laser-based fault-localization technique used in semiconductor failure analysis to identify electrically abnormal regions such as resistive shorts, leakage paths, defective vias and interconnect problems. The technique works by scanning a focused laser across an electrically biased semiconductor device. Local laser heating changes the ...

Why Dr. Morris Chang is not My Hero. A tribute to Failure Analysis Engineers

  Dr. Morris Chang is not my hero. He might be the most important person in the semiconductor industry in our lifetime, but he is not my hero. I have nothing against him. I’ve never met him and probably will never will. Instead, I meet my heroes usually after tape-out, when ...

Scanning Acoustic Microscopy (SAM) for Semiconductor Failure Analysis

Scanning Acoustic Microscopy (SAM) is a non-destructive imaging technique widely used in semiconductor failure analysis to inspect structures and interfaces hidden inside IC packages. Unlike optical microscopy, which relies on visible light, or X-ray inspection, which relies primarily on differences in material density and X-ray absorption, SAM uses high-frequency acoustic waves. This ...

Comparing Au, Pt, Ag and Cu Wire Bonding

With the creeping rise in the price of gold, many microelectronics manufacturing companies have been looking for alternatives to reduce the cost of ball bonding. Recently, the trend has been to look into the use copper wire. However, there are many drawbacks to using copper wire, including the short shelf ...

Faraday Unveils ASIC Success in Factory Automation

Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today announced that it has won and delivered several factory automation (FA) related ASIC projects, supporting real-time Ethernet, EtherCAT, Profibus, and PLC controllers. In each case, Faraday employs its value-added ASIC and IP customization service for power-performance ...

IC Decapsulation: Methods, Process and Applications

Many semiconductor failure-analysis techniques require direct access to structures that are hidden inside an IC package. The semiconductor die, bond pads, bond wires and other critical components may be completely covered by epoxy molding compound or other packaging materials. Before these structures can be examined using techniques such as optical microscopy, emission ...