Kaiserslautern, Germany – July 31, 2025 – Creonic GmbH, the leading provider of cutting-edge communications IP cores, announces the release of Version 6.0 of its DVB-S2X Demodulator IP core. This major update introduces powerful enhancements that expand the configurability and technical performance of one of Creonic’s most mature and widely ...
Many semiconductor failure-analysis techniques require direct access to structures that are hidden inside an IC package. The semiconductor die, bond pads, bond wires and other critical components may be completely covered by epoxy molding compound or other packaging materials. Before these structures can be examined using techniques such as optical microscopy, emission ...
Silicon Valley, CA (Feb 9, 2021) - Integra Technologies, a world leader in semiconductor packaging, assembly, test, characterization and related services, today announced the successful implementation of a high accuracy fiber array waveguide attachment system focused on the Silicon Photonics market. This latest set of tools is based on the double-sided HexNano ...
Integrated circuits can fail for many different reasons. Some failures originate inside the semiconductor die, while others result from packaging, manufacturing, assembly, electrical overstress or the environment in which the device operates. Common IC failure mechanisms include electrostatic discharge (ESD), electrical overstress (EOS), electromigration, dielectric breakdown, interconnect defects, corrosion, contamination, thermal ...
Scanning Electron Microscopy (SEM) is one of the most important imaging techniques used in semiconductor failure analysis. While optical microscopes remain extremely useful for initial inspection, many semiconductor defects are simply too small to characterize adequately with visible-light microscopy. SEM uses a focused beam of electrons rather than light, allowing engineers ...
Package failure analysis is the systematic investigation of defects and failures originating within semiconductor packaging, interconnects, solder connections, die attach, bond wires, redistribution layers and other structures that connect the semiconductor die to the outside system.
A semiconductor device may fail electrical testing even though the silicon itself is functioning correctly. ...
Dr. Morris Chang is not my hero. He might be the most important person in the semiconductor industry in our lifetime, but he is not my hero. I have nothing against him. I’ve never met him and probably will never will. Instead, I meet my heroes usually after tape-out, when ...
The factors affecting silicon wafer cost are numerous. From the resistivity required for different applications to the physical size of the wafers, and not least the quality grades that separate the pristine from the less perfect; each aspect intricately influences the cost.
As we embark on this explanation, we'll unwrap the ...
The NVM Express (NVMe) specification has been introduced in 2011. Five years later, it is definitely adopted as the new standard storage interface for Solid-State Drives (SSD). Even if SAS and SATA SSDs are still dominating the market (in unit shipment), the PCIe SSD market share is growing fast and ...
When a semiconductor device fails, the visible damage is not necessarily the root cause. A damaged metal line, cracked package, leaking transistor or burned bond wire may be the final result of a sequence of events rather than the original problem. The purpose of the semiconductor failure analysis process is therefore to ...
