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Germany
Creonic is the leader in ready-for-use IP cores, offering a rich product portfolio for wired, wireless, fiber and free-space optical communications.
IP Customization, Low power, small footprint Design Methodology, Integration Services on Customer FPGA Boards, System Design, Consulting
IEEE 802 Data Center and Wireless FEC , OpenZR+/ Open ROADM oFEC 800GbE, SDA, ITU High-Speed Optical Communication IP Cores, Full ETSI DVB-S2X Wideband Transmitter and Receiver, AWGN Channel, 3GPP Mobile Communications
View vendor pageOverview of Silicon-Germanium (SiGe) Technology and Historical Development Shockley's early transistor game most likely inspired the notion of fusing silicon (Si) and germanium (Ge) to create an alloy for use in transistor engineering. However, this concept has just become a reality in the last 15 years due to the challenges associated ...
With the creeping rise in the price of gold, many microelectronics manufacturing companies have been looking for alternatives to reduce the cost of ball bonding. Recently, the trend has been to look into the use copper wire. However, there are many drawbacks to using copper wire, including the short shelf ...
When an integrated circuit fails, one of the first questions is: How is the device failing electrically? A chip may exhibit excessive leakage current, a short circuit, an open connection, abnormal supply current, a parametric shift or a complete functional failure. Before engineers physically cut into the device, they usually want to ...
Nanoprobing is an advanced electrical characterization and fault-localization technique used in semiconductor failure analysis to directly investigate individual transistors, contacts, vias and interconnect structures inside an integrated circuit. Instead of relying only on package-level electrical measurements, nanoprobing allows extremely small conductive structures on a deprocessed semiconductor die to be contacted using ...
Finding the right semiconductor failure analysis lab often depends less on the laboratory's name and more on whether it has the equipment and technical expertise required for your specific failure. A package delamination problem may require Scanning Acoustic Microscopy. A suspected interconnect defect may require FIB cross-sectioning and SEM inspection. Leakage ...
Palo Alto, CA - 25 March 2025. Sarcina Technology, a global semiconductor packaging specialist, is excited to announce the launch of its innovative AI platform to enable advanced AI packaging solutions that can be tailored to meet specific customer requirements. Leveraging ASE’s FOCoS-CL (Fan-Out Chip-on-Substrate-Chip Last) assembly technology, this platform ...
UK
Seamlessly Bridging the Analogue and Digital Worlds for Tomorrow's Chiplet Solutions.
Partnership Programs, Standard Chiplet Design, Custom SoC and IP Design & Licensing, Comprehensive Design Services, Consulting
View vendor pageImagine a world where data moves at the speed of light—literally. Silicon photonics makes this possible, merging optics with the familiar silicon used in traditional electronics. This advanced technology, originating from the 1980s, stands today as a pivotal innovation in microelectronics. It offers faster data transfer rates and lower power consumption ...
Package failure analysis is the systematic investigation of defects and failures originating within semiconductor packaging, interconnects, solder connections, die attach, bond wires, redistribution layers and other structures that connect the semiconductor die to the outside system. A semiconductor device may fail electrical testing even though the silicon itself is functioning correctly. ...
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