Kaiserslautern, Germany – May 21, 2025 – Creonic GmbH, a leading provider of ready-to-use IP cores for ASIC and FPGA applications, announces the release of its new oFEC (Open Forward Error Correction) codec IP core. The solution supports next-generation optical and high-speed communication systems and is now available in both ...
Need semiconductor failure analysis services? AnySilicon helps semiconductor companies, fabless companies, IDMs, electronics manufacturers and engineering teams identify failure analysis laboratories with the equipment and expertise required to investigate IC, wafer, die and semiconductor package failures.
A good semiconductor failure analysis lab does more than operate laboratory equipment. The laboratory must ...
OBIRCH (Optical Beam Induced Resistance Change) is a laser-based fault-localization technique used in semiconductor failure analysis to identify electrically abnormal regions such as resistive shorts, leakage paths, defective vias and interconnect problems.
The technique works by scanning a focused laser across an electrically biased semiconductor device. Local laser heating changes the ...
Imagine a world where data moves at the speed of light—literally. Silicon photonics makes this possible, merging optics with the familiar silicon used in traditional electronics.
This advanced technology, originating from the 1980s, stands today as a pivotal innovation in microelectronics. It offers faster data transfer rates and lower power consumption ...
The factors affecting silicon wafer cost are numerous. From the resistivity required for different applications to the physical size of the wafers, and not least the quality grades that separate the pristine from the less perfect; each aspect intricately influences the cost.
As we embark on this explanation, we'll unwrap the ...
When an integrated circuit fails, identifying the damaged component is only part of the challenge. Engineers must determine where the failure occurred, what physical or electrical mechanism caused it, and ultimately why it happened. This requires a combination of specialized IC failure analysis techniques. Some techniques detect electrical abnormalities without physically altering ...
Getting funding for a semiconductor startup is not getting easier. According to CBIngishts, there have been fewer than 20 Angel/Seed and Series A deals in the USA in each year since 2009.
So where is all the funding channeled to? In 2013, close to a quarter of all VC funding was ...
Finding the right semiconductor failure analysis lab often depends less on the laboratory's name and more on whether it has the equipment and technical expertise required for your specific failure. A package delamination problem may require Scanning Acoustic Microscopy. A suspected interconnect defect may require FIB cross-sectioning and SEM inspection. Leakage ...
Many semiconductor failure-analysis techniques require direct access to structures that are hidden inside an IC package. The semiconductor die, bond pads, bond wires and other critical components may be completely covered by epoxy molding compound or other packaging materials. Before these structures can be examined using techniques such as optical microscopy, emission ...
