Monthly Archives: March 2014


Will more ASIC design companies cooperate with Apple and Google?

It’s no secret that Google, Amazon and Apple are heavily involved in the semiconductor industry. Apple itself is the biggest buyer of chips and estimated to buy 10% of chips sold worldwide.  Google uses Intel’s CPUs in their server farms and represent alone 4% of Intel total sales.


Both Apple and Google have decided separately to establish in-house ASIC design and production activities by hiring ASIC development engineers as well as acquiring several fabless companies.


Can it be that we are on the verge of a new and exciting era, where the largest companies in the world have discovered that off-the-shelf ICs are not sufficient for a sustainable competitive advantage, and custom-made ASICs are required? The best known example, perhaps, is Apple’s A-series CPU which is the heart of every iPhone and iPad product.

But there is more to it.  During the past 5 years, Apple has acquired several fabless companies such as Anobit, PrimeSense  and Passif. And very recently EETIMES published this news about Google ramping up ASIC development groups to target the server market.


The path taken by Google and Apple is often followed by others, and there are quite good chances that Amazon will follow and design its custom chip for the Kindle. If Facebook introduces any hardware products going forwards, they will also need to come up with their custom-made ASIC to drive new and exciting features.


So if all this makes sense, we might see more Fabless and ASIC design companies involved in helping Apple, Google, Facebook and Amazon compete with each other.


Martin Varsavsky has talked about this topic at the TechCrunch event in 2013. His speech is not focused on the semiconductor industry per se’  but he believes that sooner or later any company will engage with AGAF companies (Amazon, Google, Apple and Facebook). His speech is very insightful and important, so you might want to take a look at it here.

golden rule

My Golden Rule for Chip Production Testing

Chip production testing is probably the most underestimated task by ASIC development engineers. And yet, testing is an essential step with a direct impact on final chip cost.


Let’s start with the basics. Testing of chips is necessary because the chip manufacturing process cannot provide 100% yield. Silicon foundries and assembly houses are producing ICs but some of them consist of defects and failures, and these chips need to be screened. Therefore, every chip has to be tested before it is shipped out to the market.


Chip testing has two goals:

(1) obtain maximum test coverage so you deliver high quality ICs and

(2) keep testing time to minimum to keep costs down.


Of course, meeting these two goals simultaneously is not possible and like in real life, testing strategy involves tradeoffs. A quick example: the duration of test is directly linked to test coverage – the longer the test – the better test coverage. But if test duration increases, so does the cost per chip.


In semiconductor testing I follow a very simple guideline that I’d like to share with you. It’s my golden rule for testing strategy that worked for most projects I worked on. It combines ROI, quality, politics and time to market and most of all – it makes engineers, salespeople and marketing people happy.


Here it goes (and it’s quite complicated, so read carefully):


The chip production volume is the best indication for defining the chip test strategy. For high volume runners, I plan high NRE investment. For low volume projects – I plan low NRE investment. For medium volume, I plan medium NRE investment.


If production quantity over lifetime is high, your company can benefit a lot if you create a robust test solution that is optimized for minimum test time.  The following are a few ideas I apply for high volume runners:


Try to reduce test duration using any of the following methods:

  • Add test blocks inside the chip. For example: BIST- built it self-test, different internal loopbacks to test transmitters and receivers, internal memory tests, etc.

  • Add hardware on the test board (load board) to perform very dedicated testing to speed up the test process. This can be done by an FPGA for example.

  • Design multi-site testing (testing ICs simultaneously). With today’s advanced semiconductor testers some companies are testing 32 ICs in one go.


When it comes to the hardware that physically connects the chip or wafer to the tester — don’t settle on low quality products.  Socket or needles are extremely important. Try to get the best quality products you can buy. Why? Because if your socket wears out quickly, the tester will start losing contact with the chip-under-test, and will start reporting false failures. This means you’ll be throwing out good devices.


The same approach is valid for wafer sort. If you buy low quality needles, sooner or later the needles contact to the wafer will not be so solid, which will result in labeling some dies as faulty.


You can easily draw the conclusion for other scenarios (low volume, mid-volume) based on these examples. Or maybe you have some other ideas you can share.


The semiconductor test development companies listed on AnySilicon’s directory can help you with your next IC testing project.