Monthly Archives: April 2019

Faraday Unveils RISC-V ASIC Solution to Support Edge AI and IoT SoCs

Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today revealed that its RISC-V based ASIC platform solution has been successful in the design and mass production of next-generation edge AI and IoT system-on-chips (SoCs). This solution encompasses full system-level design services, such as RISC-V core IP integration, SoC design verification, as well as a full-featured reference design kit consisting of real-time operating system (RTOS) and peripherals drivers. Faraday has enabled mass production of RISC-V based AI SoCs on UMC’s 55ULP process, empowering particular battery-powered performances of the chips for IoT edge devices.


With more than 25 years’ experience in providing end-to-end ASIC design services, Faraday has accumulated robust CPU hardening and IP customization skills to support various ultra-low-power scenarios, including dynamic voltage and frequency scaling (DVFS), power mode switching, and fast system wake-up. Faraday also specializes in SoC software services, allowing RISC-V RTOS, software libraries, and drivers to work seamlessly with the SoC hardware to perform specific interfacing, sensing and power management functions.


“Faraday’s mass production proven RISC-V based ASIC solution is tailored for customers who want to have robust SoC design capabilities to create SoC differentiation in the burgeoning RISC-V market,” said Flash Lin, Chief Operating Officer of Faraday. “We have seen many RISC-V ASIC design opportunities, especially in a variety of edge AI, IoT/AIoT, and networking applications. We look forward to implementing more next-generation innovations to benefit our customers and the market.”


About Faraday Technology Corporation

Faraday Technology Corporation (TWSE: 3035) is a leading ASIC design service and IP provider, certified to ISO 9001 and ISO 26262. The broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDR2/3/4, low-power DDR1/2/3, MIPI, V-by-One, USB 2.0/3.1 Gen 1, 10/100/1000 Ethernet, Serial ATA, PCI Express, and programmable SerDes, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please or follow Faraday on LinkedIn.



Press Contact
Evan Ke
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Attopsemi’s I-fuse OTP Passed 3 lots of HTS and HTOL Qualification for 1,000hr on GLOBALFOUNDRIES 22FDX FD-SOI Technology

Attopsemi, an OTP IP provider, announced today that the company’s 256Kb OTP (One-Time Programmable) IP, manufactured on GLOBALFOUNDRIES (GF®) 22FDX® technology, passed 3 lots of 150°C HTS and and 125°C HTOL for 1,000 hours following the JEDEC standards. Not only all 120Mb in 3 lots of HTS/HTOL passed functionally, the cell currents did not show any variations after stresses. The defect rate is less than 0.01ppm. This is a phenomenon as most other OTPs show severely parameters shifted and tailing bits after HTS/HTOL stresses. The X/Y plots of cell current in post-stress versus pre-stress are shown in the followings:


“Other than high reliability, I-fuse™ can be programmed at 1.0V with only 1.0mA of program current, said Shine Chung, Chairman of Attopsemi, “Because of no need for charge pumps, our I-fuse™ OTP size can be only 1/4 to 1/5 of the competing OTP technologies.” “Moreover, I-fuse™ can work at wide temperature range of from -55oC to 150oC without needing any redundancies, ECC, or twin cells.” Our I-fuse™ also offers high data security and full testability unseen in any other OTPs.” This IP also passed 250oC HTS wafer-level burn-in in a previous press release.


“We sincerely appreciate all the support from GF in developing our proprietary I-fuse™ OTP technology on 22FDX,” said Shine Chung, Chairman of Attopsemi. “After many years of dedicated works and collaboration with foundries and customers worldwide, our I-fuse™ technology has finally been demonstrated as OTP of choice. We have proven that I-fuse™ can ensure high reliability with smaller size by using a fraction of program current. With our superior OTP IP, we expect to bring substantial benefits to all semiconductor communities.”


About Attopsemi Technology

Founded in 2010, Attopsemi Technology is dedicated to developing and licensing fuse-based One-Time Programmable (OTP) IP to all CMOS process technologies from 0.7um to 7nm and beyond with various silicided polysilicon and HKMG technologies. Attopsemi provides the best possible OTP solutions for all merits in small size, high quality, high reliability, low power, high speed, wide temperature and high data security. Attopsemi’s proprietary I-fuse™ OTP technologies have been proven in numerous CMOS technologies and in several silicon foundries.

CEO Talk: George Dimitropoulos of ADVEOS

This interview was held with George Dimitropoulos, CEO of ADVEOS.



Tell me about ADVEOS


ADVEOS was founded in 2015, and is a privately-held fabless company, providing ASIC design services and developing RF and analog IP cores. Adveos supports a growing international customer base, designing various technology products and infrastructure that can be found in everyday life, for example in consumer electronics, communications networks, medical equipment, etc.


Within ADVEOS, we have managed to develop a well-balanced mix of an agile run small company with the scale and execution of a global corporation. Within the first 3 years of our existence, we have grown to a team of 35 people, we have established a Tier 1 worldwide customer base and managed to demonstrate several silicon proven chips using our designs. We’ve grown into a well-established and prestigious ASIC design house in Europe.


At the same time, we’ve had 100% employee retention. We are regularly told by our customers that they enjoy the right balance between performance and high level of support they are receiving. So, they continue the co-operation not just for the performance of the circuits, but also for the quality of the support and experience working with our engineers.


When did you start ADVEOS? What were you doing before that?


The five of us – Savvas, Thanasis, Gerasimos (Jerry), Yiannis and myself – started Adveos in 2015.  We are all coming from various assignments and roles within the semiconductor industry, ranging from small start-ups to global multinational corporations, bringing significant experience in RF, Analog, Digital and Commercial domain. Although we had overlapping periods in various companies in 2’s or 3’s, we never worked in parallel as a team of 5 in the same company, prior to ADVEOS. The timing was right when we all felt the urge to become entrepreneurs and build our own company. We started Adveos with no external funding and within a very harsh financial environment – remember that Greece was under capital controls at the time – but have never looked back since. We still have complete ownership of the company and we are enjoying every moment of it.


What problem did you see that needed to be fixed? What is your approach to solving that?


It was rather unusual at the time – and probably still is – to identify independent groups with high caliber ASIC designers outside the large multinationals. Most of ASIC design teams were part of these organizations and were not open for business to the outside world. Medium or smaller size companies had very limited access to ASIC design services, since they couldn’t afford to maintain their own ASIC design teams. In several occasions, even the large multinational companies request ASIC design services from external partners, mainly due to internal restructuring, additional resourcing, acceleration of time to market for certain projects or even for cost purposes.


Our approach was to setup a team capable of addressing the demand for custom ASIC solutions, focusing on a value for money proposition for those who would like to miniaturize their electronics without the significant overhead of an internal investment for an ASIC design group.


How was the role/offering of ADVEOS changed during the recent years?


We are becoming more focused in the area of design services we are offering. Moreover, we have now the capability to develop our own RF / Analog IP cores based on a better market understanding and following closely our customers’ requirements.


What is a typical customer for ADVEOS?


Practically, any company interested in developing a CMOS/BiCMOS chip is potentially a customer for ADVEOS.


At the present time, our customer’s portfolio ranges from Tier 1 multinational corporations offering hardware solutions in the areas of computer micro-processing or high-speed networking equipment to smaller or medium sized OEMs operating in the fields of telecommunication or medical equipment.


Customers are focused on time-to-market, first-time-right, price, etc. Do you see a change in customer behaviour in recent years? Where is the focus today and why?


It is hard to identify the priority that any customer requires for a given project. Indeed, priorities change from customer to customer, sometimes they may even dynamically change in the course of a project, especially if we are talking about developments with longer timelines. However, if I had to identify the main focus for a typical ADVEOS customer, I would probably say it is time-to-market followed by specification compliance.


Are you currently hiring? What type of jobs?


We are always in constant need for Engineers with an RF, Analog, Mixed-Signal and Digital circuit design background willing to work and live in Athens, Greece. A city with a rich history, powerful culture and a great lifestyle.


What is your #1 advice for people who want to work for Adveos?


I would advise anyone (obviously, with the right skills) who would like to join us, to do so with an enthusiasm to strive and with a very strong team-player mentality. These are both very important virtues that we value as a Company and these are the very virtues that shall take him/her very far in his/her professional career.


Where can one find more information?


You may check our website or our LinkedIn company page . For job applications, please send your CV at


What is the best moment in your day?


I really love the fact that so many things happen in ADVEOS that every day can be different on its own and bring special moments. Having said that, the days I am at the office, I thoroughly enjoy the first morning coffee of the day with Jerry and Yiannis in the coffee shop round the corner: a really nice way of planning your business day ahead, and combining it with pleasant conversations from yesterday’s politics and sports news.


How do you spend your time outside working hours?


During the weekends, I try to spend as much time with my family, which I don’t really have the chance to do during the weekdays. In addition, I try to keep myself active (running, cycling, swimming), while reading a good book or watching a great movie are equally important. Last but not least, traveling is also very high on my agenda, when time is not an issue.

Proven technology significantly reduces risk, time-to-market and overall cost

Belgium, April 8, 2019 – Sofics bvba (, a leading semiconductor integrated circuit IP provider announced that it has expanded its TakeCharge® Electrostatic Discharge (ESD) and Analog IO portfolio with solutions for the TSMC 7nm FinFET process. Sofics has already verified its TakeCharge Analog IO’s and ESD protection clamps on a wide variety of processes, including CMOS, SOI and FinFET technologies across various fabs and foundries.


Sofics is a foundry independent semiconductor IP provider that has supported 60+ fabless companies worldwide with customized/specialty Analog I/Os and on-chip ESD protection. Most foundries provide I/O libraries for free. However, for several application types the general purpose I/Os introduce all kinds of limitations. Fabless companies using Sofics IP can enable higher performance, higher robustness and reduce design time and cost. The technology is silicon and product proven in more than 3000 mass produced IC-products.


Interface ESD protection in FinFET technology is challenging. The FinFET circuits fail easily under stress and the traditional ESD concepts are not effective anymore. Moreover, for advanced applications free GPIO libraries introduce limitations on the circuit performance due to excessive parasitic capacitance, leakage or voltage tolerance.

“Our specialized interface solutions enable product reliability and manufacturing yield for the leading-edge applications in the world’s most advanced foundry process”, said Koen Verhaege, CEO of Sofics. “This defines one of our key roles in the IP eco-system: reducing time-to-market and optimizing customer profit by mitigating the risk, expenses and delays of ESD re-design. The cells provide competitive advantage through improved yield, reduced silicon footprint and enable high speed, higher operating voltages and complex architectures.“

“Whether it is 0.18um CMOS or 7nm FinFet does not really matter. Fabless companies will always benefit from a shorter timeline and a lower cost combined with the confidence of a working solution”.


TakeCharge cells as well as robust I/O solutions are readily available from Sofics.



About Sofics – Sofics stands for “Solutions for ICs”. We are a foundry independent IP provider with a track record in on-chip robustness for ESD, EOS and EMC. Leveraging an extensive patent portfolio, more than 70 licensees, product proof in more than 50 processes, generates on average every day one new IC volume production release including Sofics IP.

Read more about Sofics here and here.

TSMC and OIP Ecosystem Partners Deliver Industry’s First Complete Design Infrastructure for 5nm Process Technology

TSMC today announced delivery of the complete version of its 5 nanometer (nm) design infrastructure within the Open Innovation Platform® (OIP). This full release enables 5nm systems-on-chip (SoC) designs in next-generation advanced mobile and high-performance computing (HPC) applications, targeting high-growth 5G and artificial intelligence markets. Leading Electronic Design Automation (EDA) and IP vendors collaborated with TSMC to develop and validate the complete design infrastructure, including technology files, process design kits (PDKs), tools, flows and IP, through multiple silicon test vehicles.


TSMC’s 5nm process is already in risk production and offers IC designers a new level of performance and power optimization targeted at the next generation of high-end mobile and HPC applications. Compared with TSMC’s 7nm process, its innovative scaling features deliver 1.8X logic density and 15% speed gain on an ARM® Cortex®-A72 core, along with superior SRAM and analog area reduction enabled by the process architecture. The 5nm process enjoys the benefits of process simplification provided by EUV lithography, and is making excellent progress in yield learning, achieving the best technology maturity at the same corresponding stage as compared to TSMC’s previous nodes.


TSMC’s comprehensive 5nm design infrastructure includes the full versions of the 5nm Design Rule Manual (DRM), SPICE model, process design kits (PDKs) and silicon-validated foundation and interface IP, and also supports a full range of certified EDA tools and design flows. Backed by the resources of the largest design ecosystem in the industry, TSMC’s Open Innovation Platform®, customers have already started intensive design engagements, paving the way for product tape-outs, pilot activities and early sampling.


“TSMC’s 5-nanometer technology offers our customers the industry’s most advanced logic process to address the exponentially growing demand for computing power driven by AI and 5G,” said Cliff Hou, Vice President of Research & Development/Technology Development at TSMC. “5-nanometer technology requires deeper design-technology co-optimization. Therefore, we collaborate seamlessly with our ecosystem partners to ensure we deliver silicon-validated IP blocks and EDA tools ready for customer use. As always, we are committed to helping customers achieve first-time silicon success and faster time-to-market.”



5nm PDKs and EDA Tool Certifications
The latest 5nm PDKs are now available for production design, and include device symbols, Pcells, netlisting and techfiles to enable full design flow from custom design, simulation, implementation, dummy fill, and extraction, to physical verification and signoff.


TSMC collaborated with design ecosystem partners, including Cadence, Synopsys, Mentor Graphics, and ANSYS to certify full-line EDA tools through the TSMC OIP EDA Tool Certification Program. The core of the certification program covered silicon-centric EDA tool categories including simulation, physical implementation (Custom Design, APR), timing signoff (STA, Transistor-level STA), Electromigration and IR drop (Gate-level and Transistor-level), physical verifications (DRC, LVS), to RC extractions (RCX). Through the certification program, TSMC and EDA partners enabled design tools to support TSMC 5nm design rules, ensured required accuracy, and improved routability for optimized power, performance and area (PPA) for our customers to take full advantage of TSMC’s 5nm process technology.


5nm Design Flows

On top of tool certification, TSMC also added another layer of design flow certification with EDA partners using real designs to validate integrated tool flow for both custom and digital designs. The flow certification focused on critical design implementation requirements using certified tools from respective EDA partners. Certification criteria cover tools’ feature readiness, robustness, performance, correlation between implementation and sign-off tools, and design constraints compliance with real designs. Through the comprehensive tool and flow development, enhancement, and certification, TSMC customers can implement their designs with optimized solutions, reduce design turn-around time, and strive for first-time-working silicon using TSMC’s 5nm process technology. In addition, TSMC also provided reference flows for both mobile and high-performance computing (HPC) applications which address new design methodologies to improve design quality and efficiency.


Foundation IP & 3rd party IP

TSMC’s 5nm design infrastructure provides a comprehensive IP Portfolio ready to support the needs of both the advanced mobile segment and HPC applications targeting 5nm process. The Foundation IP includes high-density and high-performance sets of standard cell libraries and memory compilers, all of which are available from TSMC and its IP ecosystem partners.


TSMC IP partners also offer interface IP cores supporting both mobile computing and HPC. IP cores such as LPDDR or MIPI PHYs are optimized for mobile solutions, whereas enterprise-dedicated DDR PHYs are optimized for HPC dedicated applications. Other IP cores, such as USB and PCIe PHYs support both segments. These 5nm IP cores are ready for design starts, and IP Silicon reports are available from TSMC and its partners.



The entire TSMC 5nm design infrastructure is available now from TSMC Online for customer downloads.


Partner Quotes

“Building upon several years of close collaborations with TSMC, we’ve advanced 5nm SoC design innovation across next-generation mobile, HPC and infrastructure application areas like AI and 5G, and have enhanced our tools with machine learning capabilities to improve power, performance and area outcomes. To further support the production delivery of TSMC’s 5nm design infrastructure, Cadence has undergone TSMC’s latest 5nm v1.0 certification process and delivered IP and integrated tools, flows and methodologies that support both traditional and cloud-based environments, including TSMC’s OIP Virtual Design Environment, to ensure that customers have a seamless user experience. Several mutual customers have successfully done 5nm production tapeouts using Cadence’s tools, flows and IP for full production development.”

Dr. Aniruth Devgan, President, Cadence

“Mentor is proud to once again partner closely with TSMC to enable our mutual customers to quickly design and deliver state-of-the-art ICs using TSMC’s industry-leading 5nm process technology,” said Joe Sawicki, executive vice president for Mentor’s IC Segment. “Our Analog FastSPICE and Calibre physical verification platforms have been in use at the 5nm node with TSMC’s early customers. The same TSMC-certified offerings are now being adopted by companies needing advanced 5nm technology to deliver innovative ICs for the mobile, high-performance computing, automotive, AI and IoT/wearable markets.”

Joe Sawicki, Executive Vice President, Mentor IC EDA

“Our strong partnership with TSMC on their 5nm process technology has spanned a broad range of design styles in an effort to successfully push and optimize performance, power and area at low voltage. An early and deep collaboration model, combined with aggressive new R&D innovations in our TSMC-certified digital, signoff and custom/analog products, enables our mutual customers to immediately and confidently engage on high-quality production 5nm design. Using Synopsys’ Fusion Design Platform and DesignWare IP, designers can achieve compressed schedules on their competitive high-performance computing designs targeting the 5G mobile and artificial intelligence markets.”

Sassine Ghazi, co-General Manager, Design Group, Synopsys Inc.


About TSMC

TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s largest dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technology and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry.


TSMC serves its customers with annual capacity of 12 million 12-inch equivalent wafers in 2019 from fabs in Taiwan, the United States, and China, and provides the broadest range of technologies from 0.5 micron plus all the way to foundry’s most advanced processes, which is 7-nanometer today. TSMC is the first foundry to provide 7-nanometer production capabilities and is headquartered in Hsinchu, Taiwan. For more information about TSMC please visit

Fabless Company Sales By Region 2018

IC Insights published its updated 2019-2023 semiconductor market forecasts and top-40 IDM and top-50 fabless IC company sales rankings in its recently released March Update, the first monthly Update to the 500-page, 2019 edition of The McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry.


Figure 1 depicts the 2018 fabless company share of IC sales by company headquarters location.  With 68%, the U.S. companies continued to hold the dominant share of fabless IC sales last year, just one percentage point less than in 2010.



semiconductor fabless sales by region

Figure 1

Since 2010, the largest fabless IC marketshare increase has come from the Chinese suppliers, which held a 13% share last year as compared to only 5% in 2010.  In 2018, four of the top five fastest growing fabless IC companies (with greater than $200 million in sales) were Chinese companies (BitMain, ISSI, Allwinner, and HiSilicon).  However, when excluding the internal transfers of HiSilicon (over 90% of its sales go to its parent company Huawei), ZTE, and Datang, the Chinese share of the fabless company IC sales drops by about half to 7%.


European companies held only 2% of the fabless IC company marketshare in 2018 as compared to 4% in 2010.  This loss of share was partly due to the acquisition of U.K.-based CSR, the second-largest European fabless IC supplier, by U.S.-based Qualcomm in 1Q15 and the purchase of Germany-based Lantiq, the third-largest European fabless IC supplier, by U.S.-based Intel in 2Q15.  These acquisitions left U.K.-based Dialog ($1.44 billion in sales in 2018) and Norway-based Nordic ($271 million in sales in 2018) as the only Europe-headquartered fabless IC suppliers in the top 50-company ranking last year.


There was only one Japanese firm in the 2018 top-50 fabless supplier ranking—Megachips, which saw its sales jump by 19% in 2018 to $760 million.  The lone South Korean company—Silicon Works, had a 17% increase in sales last year to $718 million.


Worldwide fabless IC sales increased by $8.3 billion in 2018, which represented an 8% increase from 2017.  In total, 16 of the top 50-fabless IC suppliers had better results than the global 2018 IC market increase of 14%.  Overall, 21 of the top 50 fabless IC suppliers registered double-digit growth rates last year while five companies logged double-digit declines.  Five fabless companies—China-based BitMain, ISSI, Allwinner, and HiSilicon, and U.S.-based Nvidia—registered ≥25% growth in 2018.


The fastest growing fabless IC supplier in 2018, at 197%, was China-based BitMain, which has had a very interesting past couple of years.  It should be noted that labeling BitMain an IC supplier is a bit misleading.  BitMain is an electronic system supplier of cryptocurrency mining equipment.  Since the company does not sell individual ICs on the open market, its IC “sales” are similar to those IC Insights lists for Apple, with BitMain’s IC sales essentially being the value of ICs it purchases from its sole-source foundry—TSMC.


It is estimated that BitMain held an 84% share of the $5.0 billion worldwide cryptocurrency mining equipment market in 2018.  The company had a meteoric rise in its sales over the past three years.  BitMain’s total sales were $278 million in 2016, $2.5 billion in 2017, and an estimated $4.4 billion in 2018.  The company’s equipment sales are very closely tied to the price of cryptocurrencies, especially Bitcoin.  With the crash of Bitcoin prices from $18,000 in January 2018 to $3,500 in December 2018, IC Insights estimates BitMain’s total sales went from a company-published $2.8 billion in 1H18 to $1.6 billion in 2H18.


IC Insights believes that BitMain’s steep rise and fall in cryptocurrency mining equipment sales since 2016 is responsible for the majority of the volatility of TSMC’s China-based foundry sales over the past two years (Figure 2).
TSMC sales in China

Figure 2

Overall, IC Insights believes that most of the large fabless IC suppliers will continue to do well and will help drive significant sales gains by the major IC foundries (e.g., TSMC, GlobalFoundries, Samsung, UMC, etc.).  Moreover, as the barriers to entry (i.e., high design costs, increasingly difficult access to venture capital money, etc.) rise, and fewer fabless companies are founded, IC Insights believes that the total fabless IC supplier listing will continue to grow increasingly “top-heavy” in the future.


Report Details:  The 2019 McClean Report
Additional details on IC company rankings and semiconductor market trends are provided in The McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry (released in January 2019).  A subscription to The McClean Report includes free monthly updates from March through November (including a 200+ page Mid-Year Update), and free access to subscriber-only webinars throughout the year.  An individual-user license to the 2019 edition of The McClean Report is priced at $4,990 and includes an Internet access password.  A multi-user worldwide corporate license is available for $7,990.
To review additional information about IC Insights’ new and existing market research reports and services please visit our website:


More Information Contact

For more information regarding this Research Bulletin, please contact Bill McClean, President at IC Insights. Phone: +1-480-348-1133 email:


PDF Version of This Bulletin

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